High accurate optical proximity correction under the influences of lens aberration in 0.15 μm logic process

Harazaki, Katsuhiko; Hasegawa, Yasuo; Shichijo, Y.; Tabuchi, H.; Fujii, Koichi

doi:10.1109/imnc.2000.872601

“…The distortions in optical lithography include corner rounding, pulling back at the end of the narrow line, and the wide variation of line widths. To compensate for the distortion or cancel out the interference from the neighboring light diffractions, two techniques-OPC [12,13,33] and Phase Shift Masking (PSM) [6,7,24,30] have been demonstrated to show significant improvements in sub-wavelength lithography technology. OPC works by adding or subtracting some features as serifs or line segments while PSM operates by changing the phase of the transmitted light through certain regions on the mask.…”

Section: Opc Technologiesmentioning

confidence: 99%

Multilevel full-chip gridless routing considering optical proximity correction

Chen

¹

,

Chang

²

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great flexibility. The gridless routing is much more difficult than the grid-based one because the solution space of gridless routing is significantly larger than that of grid-based one. In this paper, we present the first multilevel, full-chip gridless detailed router. The router integrates global routing, detailed routing, and congestion estimation together at each level of the multilevel routing. It can handle non-uniform wire widths and consider routability and optical proximity correction (OPC). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the famous state-of-the-art three-level routing and multilevel routing (multilevel global routing + flat detailed routing) cannot complete routing for any of the circuits. Besides, experimental results show that our multilevel gridless router can handle non-uniform wire widths efficiently and effectively (still maintain 100% routing completion for all circuits). In particular, our OPC-aware multilevel gridless router archives an average reduction of 11.3% pattern features and still maintains 100% routability for the 11 benchmark circuits.

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“…The distortions in optical lithography include corner rounding, pulling back at the end of the narrow line, and the wide variation of line widths. To compensate for the distortion or cancel out the interference from the neighboring light diffractions, two techniques-OPC [12,13,33] and Phase Shift Masking (PSM) [6,7,24,30] have been demonstrated to show significant improvements in sub-wavelength lithography technology. OPC works by adding or subtracting some features as serifs or line segments while PSM operates by changing the phase of the transmitted light through certain regions on the mask.…”

Section: Opc Technologiesmentioning

confidence: 99%

Multilevel full-chip gridless routing considering optical proximity correction

Chen¹,

Chang²

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

5

0

View full text Add to dashboard Cite

To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great flexibility. The gridless routing is much more difficult than the grid-based one because the solution space of gridless routing is significantly larger than that of grid-based one. In this paper, we present the first multilevel, full-chip gridless detailed router. The router integrates global routing, detailed routing, and congestion estimation together at each level of the multilevel routing. It can handle non-uniform wire widths and consider routability and optical proximity correction (OPC). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the famous state-of-the-art three-level routing and multilevel routing (multilevel global routing + flat detailed routing) cannot complete routing for any of the circuits. Besides, experimental results show that our multilevel gridless router can handle non-uniform wire widths efficiently and effectively (still maintain 100% routing completion for all circuits). In particular, our OPC-aware multilevel gridless router archives an average reduction of 11.3% pattern features and still maintains 100% routability for the 11 benchmark circuits.

show abstract