High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

Abstract

A: CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 × 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in 1Corrrsponding author.

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

“…The measured frequency locking range of PLL is from 320 MHz to 2.68 GHz. The highest average data rate of the detector is 3.84 Gbps, which agrees with the stringent average hit rate of the W bosons in triggerless mode [6]. The preliminary self-tests by using an internal PRBS-2 7 (Pseudo-Random Binary Sequence) generator as the data source of the serializer show it is hard to work at about 4 Gbps limited by the technology and driving capability, but can work up to 3 Gbps (see figure 9).…”

“…The in-pixel readout logic that works at the main clock of 40 MHz has a very limited area. At the same time, the digital periphery and a serializer with an internal PLL (Phase Lock Loop) are designed to be compatible with high data rate readout architecture [6].…”

“…The average trigger rate is 50 kHz, and the trigger latency is supposed 3~6 µs. The required data rates correspond to the physics case scenarios described in [6]. An interface of 160 Mbps in trigger mode is capable of meeting all these requirements.…”

“…Each pixel is recorded with a 32-bit word in the following format (see figure 10). It has 1-bit data available flag ("1" means data valid, "0" means data invalid), 8 bits timestamp, 19 bits pixel address information, and 4 bits data compression pattern [6]. A reference pattern of data has to be added to the data output to be able to decode it.…”

Readout electronics for the CEPC vertex detector prototype and beam telescope

“…The detector module of the prototype features a three-layer, double-sided design called Ladder. Each Ladder is composed of a total of ten TaichuPix-3 [6][7][8][9], a specialized MAPS chip, arranged by five in each of its two sides. Dedicated readout electronics were developed to implement the control and readout functions of the detector.…”