2021
DOI: 10.1088/1748-0221/16/09/p09020
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The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

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Cited by 10 publications
(3 citation statements)
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“…Every pixel consists of an analog front-end, a charge collection diode, a register for recording hits and logic for pixel mask orders and test pulse signals. To deal with the simulated hit rate of 120 MHz, as per the CEPC conceptual design report, the TacihuPix-3 chip is designed to achieve a maximum data rate of 3.84 Gbps in triggerless mode [6]. To handle such high data rates in the data acquisition (DAQ) system, a preliminary solution is to implement a trigger.…”
Section: Architecture Of the Vertex Detector Prototypementioning
confidence: 99%
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“…Every pixel consists of an analog front-end, a charge collection diode, a register for recording hits and logic for pixel mask orders and test pulse signals. To deal with the simulated hit rate of 120 MHz, as per the CEPC conceptual design report, the TacihuPix-3 chip is designed to achieve a maximum data rate of 3.84 Gbps in triggerless mode [6]. To handle such high data rates in the data acquisition (DAQ) system, a preliminary solution is to implement a trigger.…”
Section: Architecture Of the Vertex Detector Prototypementioning
confidence: 99%
“…In 2016, the MOST1 project (supported by the Ministry Of Science and Technology of China) initiated the research on MAPS for the CEPC vertex detector. Following MOST1, the MOST2 project was launched to develop a prototype of the vertex detector [6]. The detector module of the prototype features a three-layer, double-sided design called Ladder.…”
Section: Introductionmentioning
confidence: 99%
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