High efficiency data access system architecture for deblocking filter supporting multiple video coding standards

Abstract

This paper presents an efficient VLSI architecture of in-loop deblocking filter (ILF) with high efficiency data access system for supporting multiple video coding standards including H.264 BP/MP/HP, SVC, MVC, AVS, and VC-1. Advanced standards, such as H.264 MP/HP, SVC, and MVC, adopt Macro Block Adaptive Frame Field (MBAFF) to enhance coding efficiency which results in the performance bottleneck of deblocking filter due to complex data access requirement. This design challenge has not been discussed in previous works according to our best knowledge. Therefore, we develop a Prediction Data Management (PDM) to manage the input prediction data order of deblocking filter for different coding types (like frame/field) and multiple standards. We also design an extended output frame buffer module to solve the system bus architecture restriction (like 1K boundary and burst length) and achieve high efficiency data access by using MB-based scan order. By using these techniques, we can solve the data accessing design challenge and reduce 67% bus latency. After being implemented by using 90 nm CMOS technology, the proposed work can achieve real-time performance requirement of QFHD (3840×2160@30fps) when operated at 156MHz at the cost of 50.6K gates and 2.4K bytes local memory. The maximum operating frequency of the proposed design, i.e. 370MHz, is higher than the required real-time operating frequency so that voltage scaling may be adopted to reduce power consumption. 1

High‐speed low‐power very‐large‐scale integration architecture for dual‐standard deblocking filter

“…The proposed architecture has also been synthesised using SYNOPSYS design compiler with UMC L180 RFMM Process Zhou et al [12] Chen et al [13] Ozcan et al [11] Zhu et al [15] Shen et al [16] Li et al [ Table 2 shows the comparison of the proposed architecture with some of the existing architectures. Majority of architectures [10,12,13,21] support only H.264/AVC standard and architectures [11,[14][15][16]] support only HEVC standard, whereas only the architecture reported in [17] supports both H.264/AVC and HEVC standards. As the process technologies adopted by the existing work and the proposed work differ, normalised power [22] has been considered as a measure for comparing the present work with the existing work.…”