High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Convective scheme solution of the Boltzmann transport equation for nanoscale semiconductor devices

“…As shown in the plots, the numbers in the tail of the distribution are greater in the case of 0.9 V applied on the gate contact than they are for the case of 0.6 V applied on the gate. Ang et al [42] showed experimentally that the worst-case stress conditions occur at V g . V d .…”

“…We see in the results that as the gate voltage becomes equal to the drain voltage, the amounts of electrons in the tail increase, which in turn implies an increase in the hot-carrier damage that can occur. Ang et al [42] found conclusive experimental evidence that the worst-case stress condition is caused by the increased injection of the ''high-energy tail'' electrons into the gate oxide under such conditions. To see the effect of varying the gate voltage while holding the drain voltage constant at 0.9 V, consider Fig.…”

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

“…Because these processes must meet minimum threshold energies, HCE were not expected to be a reliability issue for the low operating voltages of modern, nanoscale CMOS technologies. However, contrary to these expectations hot carriers continue to be a concern for CMOS at or even less than 1.2 V [1]. This was predicted some time ago with the help of Monte Carlo simulations, where HCE were shown to exist in deeply scaled MOSFETs, due to electron-electron interactions (EEI) [2,3].…”

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

“…As the dimensions of the MOS transistor are scaled down, the condition for maximum hot carrier (HC) degradation shifts from drain avalanche hot-carrier stress to channel hot-carrier (CHC) stress [1][2][3]. Several researchers have studied CHC effects over a large range of both gate V g and drain voltages V d [4,5].…”

“…Several researchers have studied CHC effects over a large range of both gate V g and drain voltages V d [4,5]. According to these studies, CHC stress is the worst stress condition for a short channel device [1][2][3][4][5].…”