High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO₂ Gate Dielectric

Abstract

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

Challenges and opportunities in advanced Ge pMOSFETs

“…However, as shown in Fig. 9, the hole mobility reduces to the relaxed Ge values for short channel transistors, indicating already one of the limitations [9]. A record low EOT of 0.85 nm has been reported for 70 nm Ge pMOSFETs in shallow trench isolation silicon wafers [64], whereby a smaller low-field mobility has been achieved.…”

“…In addition, the impact of strain on the low-field hole mobility of p-channel Ge devices has been documented extensively in the literature [9,[48][49][50][51][52]. The question is, however, if the low-field mobility still has an impact on deeply scaled transistors which are velocity saturated in stationary operation.…”

“…Low-field hole mobility corrected for the parasitic series resistance as a function of gate length. Also included is the hole mobility obtained on strained SiGe channel pMOSFETs [130] (after Mitard et al [9]). more detail, with the emphasis on their scaling potential.…”

“…8 has been fabricated, yielding a long-channel hole mobility of 290 cm 2 /Vs [9]. However, as shown in Fig.…”

“…In other words, high channel mobility semiconductors will most likely play a key role in sub-14 nm CMOS technology nodes [6]. In spite of the fact that large progress has been made in the meantime, with record performance for 65 nm [7] and 70 nm [8] Ge-on-Si pMOSFETs, 65 nm strained-Ge (sGe) pMOSFETs [9] and 30 nm Germanium-on-Insulator (GeOI) devices [10], there remain a few important issues and hurdles to be overcome in order to fully exploit the potential offered by the high carrier mobility of germanium.…”