High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

Al-Ameri

IEEE Trans. Electron Devices

et al. 2015

Abstract-In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

mentioning

confidence: 99%

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Al-Ameri

IEEE Trans. Electron Devices

et al. 2015

“…By that, it decreases the variability [8], and it will have better matching for short channel devices. Also, the absence of channel doping and pocket implants in the fully depleted transistor produces lower noise specifications and higher gains when compared to bulk technologies.…”

Section: -Nm Utbb Fd-soimentioning

confidence: 99%

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

Mohsen¹,

Harb²,

Deltimple³

et al. 2017

Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers' applications.

“…Fully depleted (FD) SOI transistors with undoped channels are ideally suited for low power applications [21]. Substrates for FD devices require very thin Si films, of the order of 20 nm with the uniformity range of <1 nm.…”

Section: Ecs Transactions 19 (4) 3-14 (2009)mentioning

confidence: 99%

SOI Technology Driving the 21st Century Ubiquitous Electronics

Celler¹

2009

ECS Trans.

Electronics is expanding into all spheres of our life, spreading far beyond computer systems, mobile telephony, and personal computers -into games, appliances, navigation systems, at-home health diagnostics, a variety of smart sensors at home, in cars and in the workplace. RFID chips are becoming integrated into paper documents, and various sensors are likely to be included in our clothing. Silicon-on-Insulator (SOI) based technology plays a growing role in many of these applications.