High-level asynchronous system design using the ACK framework

Jacobson, Hans; Brunvand, Erik; Gopalakrishnan, G.; Kudva, P.

doi:10.1109/async.2000.836975

Cited by 16 publications

(6 citation statements)

References 31 publications

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“…3 Others important milestones, using novel architectures, include the counterflow pipeline processor at Sun Microsystems Laboratories, 7 an asynchronous outoforder architecture featuring precise exceptions at University of Utah, 8 a superpipelined multimedia processor at Sharp, 9 the Post Office communication coprocessor at HP Laboratories, 10 and a lowpower sensornetwork processor from Cornell University. 11 Asynchronous design has also been used as a foundation for largescale interprocessor communication, including the Torus routing chip, 12 FLEETzero at Sun Microsystems Laboratories, 13 and the terabitrate commercial crossbar switches of Intel/Fulcrum. 14 Finally, the recent surge of interest in cognitive computing is exemplified by several recent neuromorphic processors IBM's TrueNorth, 15 Stanford University's Neurogrid (Boahen's group), 16 and University of Manchester's SpiNNaker 17 (Furber's group) , all of which use fullyasynchronous interconnection networks to integrate massivelyparallel architectures with thousands (and, eventually, millions) of processing elements.…”

Section: Sidebar I: Processors and Architecturementioning

confidence: 99%

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Asynchronous Design—Part 2: Systems and Methodologies

Nowick

Singh

2015

IEEE Des. Test

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Section: Sidebar I: Processors and Architecturementioning

confidence: 99%

“…11 A system is specified at a procedural level using Standard Verilog HDL, with an addon package of asynchronous channel abstractions, and the compiler maps it to distributed asynchronous control and datapath blocks. Three controller types are supported: burstmode, 2 macromodular, 12 and microprogrammed control.…”

Section: High-level Synthesismentioning

confidence: 99%

Asynchronous Design—Part 2: Systems and Methodologies

Nowick

Singh

2015

IEEE Des. Test

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“…These tools have been used to create significant designs, such as the SPA [27] using Balsa and a low power pager [28] using Tangram. Another approach is that used by the ACK Framework [29], that partitions designs specified using Verilog [30] into separate control and datapath parts. The controller is synthesized using 3-D, while the datapath is synthesized using standard commercial synthesis tools.…”

mentioning

confidence: 99%

A behavioral synthesis system for asynchronous circuits

Sacker

Brown

Rushton

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional units); and 3) binding (the mapping of the functional units onto physical cells). Optimization is usually achieved by intelligent manipulation of these three steps in some way. Key to the operation of such a system is the (automatically generated) control graph, which is effectively a complex sequence generator controlling the passage of data through the system in time to some synchronizing clock. The maximum clock speed is dictated by the slowest time slot. (This is the timeslot containing the longest combinational logic delay.) Timeslots containing quicker (less) logic will effectively waste time: the output of the combinational logic in the state will have settled long before the registers reading the data are enabled. If we allow the state to change as soon as the data is ready, by introducing the concepts of "ready" and "acknowledge," the control graph becomes a disjoint set of single-state machines-it effectively disappears, with the consequence that the timeslot-timeslot transitions become self controlling. Having removed the necessity for the timeslots to be of equal duration the system becomes selftiming: asynchronous. This paper describes a behavioral asynchronous synthesis system based on this concept that takes as input an algorithmic description of a design and produces an asynchronous structural implementation. Several example systems are synthesized both synchronously and asynchronously (with no modification to the high level description). In keeping with the well-established observation that asynchronous systems operate at average case time complexity rather than worse case, the asynchronous structures usually operate some 30% faster than their synchronous counterparts, although interesting counterexamples are observed.

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“…Another way of synthesizing asynchronous systems is the asynchronous logic synthesis approach [64] [65] [89] [90]. In this approach, a high-level description of the design is partitioned into its control and datapath components.…”

Section: Logic Synthesis Approachmentioning

confidence: 99%

Design methodologies for low-power asynchronous-logic digital systems

Law¹

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Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks. Three main contributions are made in this thesis to the design of asynchronous pipelines with low asynchronous control overheads. First, a synthesis method for asynchronous pipelines is proposed that adopts a coarse-grain approach to the synthesis of asynchronous control networks, thereby leading to low asynchronous control overhead pipelines. It also has the advantages of offering a largely transparent modeling style for asynchronous communication and ease for integration into the conventional synchronous design flow. The efficacy of the proposed synthesis method is demonstrated through the design of a Reed-Solomon error detector and an interpolated finite-impulse-response filterbank-the simulated circuit implementations based on the proposed synthesis method dissipate on the average 31% less energy than those implemented by comparable reported synthesis methods. Second, two optimization methods are proposed for reducing the circuit area and power dissipation of asynchronous control networks while satisfying pipeline throughput constraints. The first proposed optimization method-handshake component fusion-is a form of peephole optimization that iteratively selects a pair of handshake components that share input channel sources or output channel destinations and replaces them with a single component. The second proposed optimization method-optimal decoupling-searches for the optimal mix of handshake components of different degree of concurrency in a given asynchronous control network with the objective of incurring the least circuit area and power dissipation for the control network, while satisfying a throughput constraint. The proposed optimization methods are applied on three designs and are found to reduce the asynchronous control networks' transistor count and energy dissipation by, on the average, 28% and 36%, respectively. A fundamental requirement of the proposed optimization methods is that the minimal-support S-invariants for the Petri net models of the asynchronous control networks are recomputed at each optimization iteration. vii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Arising from the fundamental requirement mentioned above, the third main contribution of the thesis is a fast and memory-efficient algorithm for computing all minimal-support S-invariants for ordinary Petri nets. Based on a large number of test problems, the proposed algorithm is demonstrated to be at least 2.2x faster and 1.8x more memory efficient than reported algorithms. The proposed synthesis method, ...

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High-level asynchronous system design using the ACK framework

Cited by 16 publications

References 31 publications

Asynchronous Design—Part 2: Systems and Methodologies

Asynchronous Design—Part 2: Systems and Methodologies

A behavioral synthesis system for asynchronous circuits

Design methodologies for low-power asynchronous-logic digital systems

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