High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Chen, Deming; Cong, Jason; Fan, Yiping; Zhang, Zhiru

doi:10.1109/aspdac.2007.358040

Cited by 49 publications

(29 citation statements)

References 25 publications

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“…At the high-level synthesis stage, power estimation has been done to drive low-power resource allocation and binding techniques [6]. At the preplacement stage, work has been done to predict interconnect wirelength and delay [8,13].…”

Section: Early Delay/power Predictionmentioning

confidence: 99%

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Shum

Anderson

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.

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Section: Early Delay/power Predictionmentioning

confidence: 99%

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Shum

Anderson

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…In [20], the switching activity characteristics of the functional units were pre-characterized and used during lowpower synthesis targeting FPGAs. In [5], a low-power, simultaneous resource allocation and binding algorithm for FPGAs was presented, and included a high-level power estimator. In [3] and [4], the authors presented a simulated annealing-based algorithm which carried out high-level synthesis subtasks simultaneously, targeting FPGAs for lowpower, called LOPASS.…”

Section: Related Workmentioning

confidence: 99%

FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Cromar

Lee

Chen

2009

Proceedings of the 46th Annual Design Automation Conference

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Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, highlevel binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in [6]. High-level binding results are converted to VHDL, and synthesized with Altera's Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera PowerPlay Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power highlevel synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FPGAs that considers glitch power.

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“…This power model has been enhanced to support FPGAs with a programmable supply voltage [37] and programmable threshold voltages [38]. In [13][25] [52], high-level FPGA power models that use macro-models to estimate power are described. These models characterize the power consumption of various FPGA components, such as adders, multipliers, and programmable logic, for lowpower high-level synthesis or design space exploration.…”

Section: Fpga Power Modellingmentioning

confidence: 99%