High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Novel Damascene Gate Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by In situ Arsenic- and Boron-Doped Epitaxy

“…8, SCE are improved with a shallow junction, and the gate length at I off ¼ 100 nA/mm increases. 8,9) This means that the gate length at I off ¼ 100 nA/mm is a barometer of SCE. In this experiment, the value of the I off at a long gate length of both conventional and GORES MOSFETs are same.…”

“…Generally, as the gate length at I off ¼ 100 nA/mm decreases, R sd increases, and I on at a constant I off decreases. 8,9) In conventional nMOSFETs, the I on at I off ¼ 100 nA/mm decreases as the gate length at I off ¼ 100 nA/mm decreases. In GORES nMOSFETs, the gate length at I off ¼ 100 nA/mm was about 40 nm in this epitaxial condition, and with an increase in impurity concentrations, the I on increases.…”

High-performance bulk CMOS technology for 65/45nm nodes

“…We optimized the process conditions for both a STI nitride liner and a CES-SiN film to maximize the device performance. In stage III, short channel effects and mobility were improved by using a low temperature sidewall and optimizing the gate oxynitride conditions [7]. In stage IV in 2004, enhanced process induced strain using a laminated CES-SiN was added [4].…”

Degradation of current drivability of Schottky barrier source/drain transistors induced by high-k gate dielectrics and possible measures to suppress the phenomenon

“…As a result of this trend toward miniaturization, many devices with a gate electrode shorter than 100 nm have been reported and even normal operation of sub-10 nm gate length devices at room temperature has been reported [1][2][3][4][5][6][7]. According to this trend, quite high current drivability under low power supply voltage is required for transistors.…”