2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)
DOI: 10.1109/icsict.2001.981426
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High performance 70 nm CMOS device and key technologies

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“…The thin gate oxide RF PDSOI nMOSFETs were fabricated on SIMOX (separation by implantation of oxygen) wafers with an SOI film (p-type <100>, 20 Ω) thickness of 200 nm and a buried oxide layer of 400 nm. A summary of the major processing steps of the technology, which are based on the platform of 0.1 µm CMOS technology developed by the Institute of Microelectronics of Chinese Academy of Sciences [15] , is given as follows. Prior to the device fabrication, a LOCOS (local oxidation of silicon) approach was employed to isolate the MOSFETs; after that, maskless BF + 2 ion implants with energy 80 keV and dose 2 × 10 12 cm −2 and B + ion implants with energy 70 keV and dose 4×10 13 cm −2 were employed for front gate threshold voltage adjustment and anti-punch through purpose, respectively.…”
Section: Methodsmentioning
confidence: 99%
“…The thin gate oxide RF PDSOI nMOSFETs were fabricated on SIMOX (separation by implantation of oxygen) wafers with an SOI film (p-type <100>, 20 Ω) thickness of 200 nm and a buried oxide layer of 400 nm. A summary of the major processing steps of the technology, which are based on the platform of 0.1 µm CMOS technology developed by the Institute of Microelectronics of Chinese Academy of Sciences [15] , is given as follows. Prior to the device fabrication, a LOCOS (local oxidation of silicon) approach was employed to isolate the MOSFETs; after that, maskless BF + 2 ion implants with energy 80 keV and dose 2 × 10 12 cm −2 and B + ion implants with energy 70 keV and dose 4×10 13 cm −2 were employed for front gate threshold voltage adjustment and anti-punch through purpose, respectively.…”
Section: Methodsmentioning
confidence: 99%