High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

Abstract

A dual-gate field-effect transistor (FET) based on the same single indium-doped CdSe nanowire using Si3N4 and SiO2 as top- and back-gate dielectrics, respectively, was fabricated. This dual-gate FET enabled direct comparison of the device performance of FETs in both top- and back-gate configurations. Remarkably, the field-effect mobility, peak transconductance, and I on/I off ratio of the Si3N4 top-gate FET were 52, 142, and 2.81 × 105 times larger than the respective values of the SiO2 back-gate FET. Meanwhile, the threshold voltage and the subthreshold swing of the top-gate FET decreased to −1.7 V and 508 mV/decade, respectively, which are better than the best values ever obtained in FETs based on II−VI semiconductor nanomaterials including CdSe nanowires. The roles of device configurations and gate materials in the FET characteristics and the evaluation of electronic and transport properties of nanostructures based on that were discussed. Two kinds of basic logic circuits, “AND” and “OR”, were constructed with the top-gate transistors, which could also utilize light-input to realize a phototransistor action to take advantage of its photoresponse properties.

One-dimensional II–VI nanostructures: Synthesis, properties and optoelectronic applications

“…The electron mobility obtained from top-gate configuration is closer to that reported for CdSe single crystals, and thus is believed to be more reliable, reflecting the high-quality single-crystal nature of the CdSe:In NWs. The work demonstrates the need of a proper fabrication protocol of FETs for accurate evaluation of the electronic characteristics of the nanostructures [154].…”

“…He et al have fabricated a dual-gate nano-FET based on the same single In-doped CdSe NW using non-oxide highSi 3 N 4 and SiO 2 as top-and back-gate dielectrics, respectively [154]. The dual-gate FET minimized materials-dependent property fluctuation and enabled direct comparison of the device performance of FETs in both top-and back-gate configurations.…”

“…Most nano-FETs are constructed in a simple back-gate configuration with SiO 2 as the dielectric layer. However, as demonstrated in [154], the 'real' overall electronic and transport properties of the nanostructures studied cannot be evaluated reliably, and confusing results may be obtained. For example, the electron mobility of the same NW deduced from the FET in top-gate configuration is two orders of magnitude lager than that from SiO 2 back-gate configuration.…”

“…Wu et al reported high-performance nanoinverters with a voltage gain up to 1000 based on CdS NR MOSFET with high-HfO 2 dielectric [163]. Recently, He et al reported the realization of logic circuits by combing two top-gate CdSe:In NW FETs, which are also capable of incorporating of the inherent photoresponse properties of CdSe NWs [154]. The CdSe:In NWs showed high sensitivity to visible light, and illumination using an incandescent light source increased the threshold voltage of the transistor, as depicted in Fig.…”

Field-Effect Transistors from Lithographically Patterned Cadmium Selenide Nanowire Arrays

“…These output characteristics are consistent with enhancement mode operation for an n-type channel, 6 just as previously reported for FETs prepared from polycrystalline CdSe films 18−21 and single crystalline CdSe nanowires. 25,22,26,23,27,24 Transfer characteristics for the same two devices shown in Figure 3a from 2.5 20 to 6.7 V 18 (Table 1). This performance pertains to devices prepared from undoped CdSe.…”