High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA

Hsieh, Chih-Cheng; Wu, Chung-Yu; Sun, Tai‐Ping; Jih, Far-Wen; Cherng, Ya-Tung

doi:10.1109/4.705357

Cited by 43 publications

(6 citation statements)

References 11 publications

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“…This arrangement is essential to realize large format array with small pixel pitch. The source follower FET, M sf1 , the sample FET, M sh , the row parasitical bus capacitor C bus1 , the four-FET cascode current mirror with the current ratio of 1 which can reduce the effect of the input voltage difference across the non-uniformity row parasitic bus capacitor C bus1 , and increase the current mirror accuracy during integration [5].…”

Section: The Shared Off-irfpa Integration and Sample Stagementioning

confidence: 99%

“…Compared with the readout stricture in papers [5,6], in which, the integration and readout is in a cascode way. When a row is selected, different pixels in that row doesn't start to integrate at the same time.…”

Section: Circuit Operation and Comparisonmentioning

confidence: 99%

“…The readout timeT ro is equal to N • T csel , about 64 µs, only 6.4% of the integration time 1 ms. And because the frame time is composed of readout time and integration time (as shown in figure 8), so the frame frequency of the CSS ROC is about twice of that of BGMI structure to the same integration time. Also the output waveforms of the ROCs in the papers [5,6] are separate, instead of boxcar. Then the pulse width of the AD sample signal should be half of that of the column select signal.…”

Section: Circuit Operation and Comparisonmentioning

confidence: 99%

“…Consequently, it is desirable to suppress the background current to improve detection sensitivity, dynamic range, and application range. Generally, background suppression can be realized by using techniques such as charge-domain background suppression circuit, currentmemory-based background suppression circuit [3,4] and BGMI [5]. Though BGMI can realize background current suppression per row or column, this circuit requires a perfect voltage reference.…”

Section: Introductionmentioning

confidence: 99%

“…And the readout time is too long, just equal to the integration time, which will reduce the frame frequency very seriously, especially in the case of small integration current and long integration time, (iii) the output waveforms of the ROCs in the papers [5,6] are separate, instead of boxcar. Then the pulse width of the AD sample signal has to be half that of the column select signal.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A novel CMOS readout circuit for large format IRFPA with background current storage suppression

Zhang

Yuan

Huang

et al. 2003

Semicond. Sci. Technol.

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In this paper, we propose a novel readout circuit based on a buffered-direct-injection structure. In this new readout circuit, all the pixels in one row can start to integrate simultaneously. And the readout time can be reduced by as much as 94%. Since readout time in many conventional readout circuits contributes to half of the total row selection time, it is directly proportional to the total frame time. And the output waveform is boxcar, which is very easy to AD convert. In addition, one current storage cell is added into the readout circuit to achieve in-pixel background current suppression to remove the background component inherent in each pixel output. To increase the current mirror accuracy and the integration dynamic range, a cascode current mirror is also adopted in the readout circuit. SPICE simulation results have shown that the proposed readout circuit can achieve high charge sensitivity and resolution in a large format IRFPA with small pixel size.

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Section: The Shared Off-irfpa Integration and Sample Stagementioning

confidence: 99%

Section: Circuit Operation and Comparisonmentioning

confidence: 99%

Section: Circuit Operation and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel CMOS readout circuit for large format IRFPA with background current storage suppression

Zhang

Yuan

Huang

et al. 2003

Semicond. Sci. Technol.

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show abstract

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

Zhang

Yuan

Huang

et al. 2004

J. of Electron.(China)

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CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications

Yao

Zhao

2010

Circuits Syst Signal Process

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A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered 0.35 µm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed circuit is more than 99%. The background suppression level is tunable between 8 nA-1.5 µA, and the background suppression uniformity is as high as 100%. A unit-cell occupies a 10 µm × 15 µm area and consumes less than 0.07 mW power.

show abstract

High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA

Cited by 43 publications

References 11 publications

A novel CMOS readout circuit for large format IRFPA with background current storage suppression

A novel CMOS readout circuit for large format IRFPA with background current storage suppression

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications

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