High-Performance Hardware Implementation for RC4 Stream Cipher

Sengupta, Satarupa; Chattopadhyay, Anupam; Sinha, Koushik; Maitra, Subhamoy; Sinha, Bimal K.

doi:10.1109/tc.2012.19

Cited by 61 publications

(56 citation statements)

References 6 publications

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“…S.S Gupta [21] presents "High Performance Hardware Implementation". The paper is published in IEEE Transactions on Computers [Volume 62, issue 4].…”

Section: Related Workmentioning

confidence: 99%

Parc4-I: Parallel Implementation of Enhanced RC4A Using Pascs and Loop Unrolling Mechanism

Handa¹,

Kapoor²

2015

CAIJ

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“…S.S Gupta [21] presents "High Performance Hardware Implementation". The paper is published in IEEE Transactions on Computers [Volume 62, issue 4].…”

Section: Related Workmentioning

confidence: 99%

Parc4-I: Parallel Implementation of Enhanced RC4A Using Pascs and Loop Unrolling Mechanism

Handa¹,

Kapoor²

2015

CAIJ

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“…RC4 Algorithm RC4 stream cipher [8] was designed by Ron Rivest for RSA security of data. It consists of substitution(S)-box S, an array of length M , every position of S can store 1 byte of information.…”

Section: Cryptography Algorithmsmentioning

confidence: 99%

“…Key scheduling algorithm itself consists of two sub-stages, namely Initialization and Key setup. The steps and process of KSA algorithm 1, using the toeplitz hash function and its significance is elucidated below [8].…”

Section: Cryptography Algorithmsmentioning

confidence: 99%

FPGA implementation of stream cipher using Toeplitz Hash function

Pal

Pandian

Ray

2014

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Hardware efficient stream ciphers and hash functions are widely used in cryptographic applications. The onewayness and low hardware complexity of hash function make it a good candidate for authentication operation of crypto-systems. On the other hand, stream ciphers are being widely used in the domain of cryptology. Generally, these stream ciphers use static key stream for the crypto process. In this work, we propose a hash function based key generator and integrate the hash function based key generation with the RC4 stream cipher block so as to provide dynamic key to the RC4's encryption system thus realizing a robust security hardware prototype. The proposed method is designed for 5-bit hash key and stream cipher using Verilog HDL and simulated using Xilinx ISE 14.2 simulator. Further the design implementation has been done on the commercially available Xilinx Spartan 3E fg320-4 FPGA device. The excellence of the generated random key value by our proposed method is validated using the statistical tests proposed by National Institute of Standard and Technology (NIST).

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“…The seed changes for each run of the PRSG with each seed corresponds to a unique output sequence. Stream ciphers are heavily used in wireless communication and restricted resources applications such as 3GPP LTE-Advanced security suite [26], network protocols such as SSL, TLS, WEP and WPA [27], RFID tags [19], and bluetooth [4], to name some.…”

Section: Introductionmentioning

confidence: 99%

New Implementations of the WG Stream Cipher

El-Razouk

Reyhani-Masoleh

Gong

2014

IEEE Trans. VLSI Syst.

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This paper presents two new hardware designs of the WG-128 cipher, one for the multiple output version (MOWG), and the other for the single output version (WG), based on type-II optimal normal basis (ONB) representation. The proposed MOWG design uses signal reuse techniques to reduce hardware cost in the MOWG transformation, while it increases the speed by eliminating the inverters from the critical path. This is accomplished through reconstructing the Key and Initial Vector (IV) loading Algorithm (KIA) and the feedback polynomial of the Linear Feedback Shift Register (LFSR). The proposed WG design uses properties of the trace function to optimize the hardware cost in the WG transformation. The ASIC and FPGA implementations of the proposed designs show that their areas and power consumptions outperform the existing implementations of the WG cipher.

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High-Performance Hardware Implementation for RC4 Stream Cipher

Cited by 61 publications

References 6 publications

Parc4-I: Parallel Implementation of Enhanced RC4A Using Pascs and Loop Unrolling Mechanism

Parc4-I: Parallel Implementation of Enhanced RC4A Using Pascs and Loop Unrolling Mechanism

FPGA implementation of stream cipher using Toeplitz Hash function

New Implementations of the WG Stream Cipher

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