2015 IEEE International Symposium on Circuits and Systems (ISCAS) 2015
DOI: 10.1109/iscas.2015.7169275
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High performance IP core for HEVC quantization

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Cited by 4 publications
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“…In hardware reduction methods, the motion estimation (ME) technique based on pipelined design and rapid computing of the minimum sum absolute difference (SAD) on FPGA are introduced to speed up computation [6][7] [8][9] [10]. Moreover, the hardware efficiencies of Q reduce the computation complexity [11] [12]. This paper proposes a highly efficient video encoding, named as SATvideo coding, optimized for satellites' limited hardware W resources and power and also achieves the target compression ratio (CR) and acceptable [13] peak signal-tonoise ratio (PSNR), based on hardware resource reduction with high-quality decompressed remotely sensing video.…”
Section: Introductionmentioning
confidence: 99%
“…In hardware reduction methods, the motion estimation (ME) technique based on pipelined design and rapid computing of the minimum sum absolute difference (SAD) on FPGA are introduced to speed up computation [6][7] [8][9] [10]. Moreover, the hardware efficiencies of Q reduce the computation complexity [11] [12]. This paper proposes a highly efficient video encoding, named as SATvideo coding, optimized for satellites' limited hardware W resources and power and also achieves the target compression ratio (CR) and acceptable [13] peak signal-tonoise ratio (PSNR), based on hardware resource reduction with high-quality decompressed remotely sensing video.…”
Section: Introductionmentioning
confidence: 99%