High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Abstract

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

“…Thus, the number of pipeline stages required is very small than that for voltage mode signaling. The power consumption of this mode of signaling is also lesser than that of voltage mode signaling [49]. ii.…”

“…Current-mode signaling: Current-mode signaling [48] in NoC link reduces the delay of long wires significantly as compared to voltage-mode signaling [49]. Thus, the number of pipeline stages required is very small than that for voltage mode signaling.…”

A Survey Addressing on High Performance On-Chip VLSI Interconnect

“…Therefore, in order to save power, three current levels are required, two to differentiate between consecutive same symbols transmissions and third one is, zero current level to indicate the wire is idle were proposed in [23]- [25]. Differential current signaling proposed by Atul Maheshwari, Wayne Burleson [15] occupies more routing area Vs repeater.…”

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

“…Then, the voltage signals V x+x are compared with two logical threshold voltages V th2.5 and V th3. 5 , respectively in the voltage comparators which are designed by using a differential-pair circuit. The outputs TH25 and TH35 of the voltage comparators are inputs for the C-element.…”