High performance package designs for a 1 GHz microprocessor

Hasan, A.; Sarangi, A.; Baldwin, Chris; Sankman, Robert; Taylor, G.

doi:10.1109/ectc.2000.853323

Cited by 4 publications

(1 citation statement)

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“…Figure 5 shows the design of package capacitors connection that results in the most optimal reduction of loop inductance through mutual inductance cancellation between the planes and vias. In this example, the capacitors are placed on the pin side of the 6-layer FC-PGA package [7]. The extension of the VCC capacitor pad under the capacitor towards the GND pad and placement of micro-vias for connection from L6 to L5 layers under the capacitor lead to very efficient mutual inductance cancellation of the charge flowing through the capacitor plates and package layers.…”

Section: Figure 4: Eavp Conceptualized Design Of Power Networkmentioning

confidence: 99%

Package capacitors impact on microprocessor maximum operating frequency

Waizman

Chung

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

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This paper discusses the behavior of microprocessor (CPU) maximum operating frequency (FMAX) under various conditions. In specific, the impact of voltage and temperature on the CPU FMAX for a gate delay dominated design vs. an RC-interconnect delay dominated design are described. As voltage tolerance is reduced through proper design placement of package capacitors, and using the optimal amount of capacitance and resistance (ESR) for the package capacitors, the CPU FMAX increases. IntroductionThe increase in operating frequency and power consumption of CPU, coupled with the reduction in operating voltage poses significant challenge to the power delivery network design for the CPU core operation. To satisfy the power hungry high-speed circuits of a CPU, it is increasingly popular to place discrete capacitors on the microprocessor package to deliver the charge needed in a fast response time. The methodology to the design and analysis of effective onpackage capacitors has been previously discussed in [1,2] and the algorithm to design a robust power delivery network discussed in [3]. As described previously in [1,2], the reason for placing capacitors on the CPU package is to provide a stable power delivery network, especially at the higher frequency regime, which helps to reduce voltage tolerance.The intent of this paper is to illustrate and discuss how package capacitors enable a more stable power delivery network and increases the CPU FMAX. In Section 0 of this paper, we will illustrate how smaller voltage tolerance enables higher VCC voltage, and as a result, the CPU achieves higher FMAX. However, the amount of FMAX increase due to package capacitors contribution depends highly on the semiconductor process, circuit design, interconnect design, and operating temperature. Section 0 explores these complex relationships and their impact on CPU FMAX. Section 0 discusses design methodology to achieve a low impedance resonant free power network. This methodology leads to optimized amount of capacitance and resistance (ESR) for the package and mother-board (MB) capacitors to maximize FMAX.Finally, Section 0 presents the results that demonstrate the effectiveness of the design methodology presented and the resulting improvement in FMAX.

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Section: Figure 4: Eavp Conceptualized Design Of Power Networkmentioning

confidence: 99%