High-Performance Quasi-Monte Carlo Financial Simulation

Tian, Xiang; Benkrid, Khaled

doi:10.1145/1862648.1862656

Cited by 41 publications

(23 citation statements)

References 8 publications

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“…By exploiting the massive parallelism, FPGA implementation performs much faster than general purpose processor or GPU implementation [15]. Thus, FPGA is a promising implementation technology for not only integer arithmetic [3], but also packet classification.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

Sun

Prasanna

2011

2011 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet field in the first phase followed by the second phase where the results from the first phase are combined. However, the primary challenge in implementing this high-level approach lies in the second phase, i.e. how to efficiently combine the results of the single field searches. In this paper, we propose a systolic-array-based architecture on FPGA focusing on the combining techniques in phase two. The proposed approach exploits the rich logic resources on FPGA and achieves high throughput by deeply pipelining the architecture. We show the area analysis of the design to demonstrate the efficiency in on-chip resource usage. We also experimentally evaluate the impact of the size of the input ruleset and number of matching rules from first phase on the performance of our design. We compare our design against the Bit Vector algorithm, another decomposition-based classification method, and demonstrate that our design is more efficient with respect to logic resource usage and is feasible for large rulesets. Post place and route result using a state-of-the-art FPGA device shows that the design can sustain a throughput of 107 Gbps, for a ruleset consisting of up to 64K rules.

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Section: Introductionmentioning

confidence: 99%

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

Sun

Prasanna

2011

2011 International Conference on Reconfigurable Computing and FPGAs

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“…Monte Carlo simulation is a useful tool to solve complex problems [12,13]. We have developed an option pricing application using Monte Carlo simulation.…”

Section: Monte Carlo Simulationmentioning

confidence: 99%

Programming framework for clusters with heterogeneous accelerators

Tsoi

Tse

Pietzuch

et al. 2010

SIGARCH Comput. Archit. News

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We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources productively and efficiently. The distributed application is highly modularized to support dynamic system configuration with changing types and number of the accelerators. Multiple layers of communication interface are introduced to reduce the overhead in both control messages and data transfers. Parallelism can be achieved by controlling the accelerators in various schemes through scheduling extension. The framework has been used to support physics simulation and financial application development. We achieve significant performance improvement on a 16-node cluster with FPGA and GPU accelerators.

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“…Hardware accelerators assist central processing units (CPUs) in speeding up computations of complex algorithms in various fields, such as video/image processing (Yamaoka et al, 2006;Jan et al, 2015;Taibo et al, 2011), signal processing (Lee et al, 2013) and various mathematical calculations (Tian and Benkrid, 2010;Okuyama et al, 2012;Rostrup et al, 2013). Graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) are two types of dominantly used hardware accelerators (Chung et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

Wang

Bolić

Parri

2017

IJHPCN

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This paper presents an ameliorated design of pvFPGA, which is a novel system design solution for virtualising an FPGA-based hardware accelerator by a virtual machine monitor (VMM). The accelerator design on the FPGA can be used for accelerating various applications, regardless of the application computation latencies. In the implementation, we adopt the Xen VMM to build a paravirtualised environment, and a Xilinx Virtex-6 as an FPGA accelerator. The data transferred between the x86 server and the FPGA accelerator through direct memory access (DMA), and a streaming pipeline technique is adopted to improve the efficiency of data transfer. Several solutions to solve streaming pipeline hazards are discussed in this paper. In addition, we propose a technique, hyper-requesting, which enables portions of two requests bidding to different accelerator applications to be processed on the FPGA accelerator simultaneously through DMA context switches, to achieve request level parallelism. The experimental results show that hyper-requesting reduces request turnaround time by up to 80%.Keywords: field-programmable gate array; FPGA; hardware accelerator; virtualisation; hyperrequesting; streaming pipeline; DMA context switch.Reference to this paper should be made as follows: Wang, W., Bolic, M. and Parri, J. (2017) 'pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing', Int.

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High-Performance Quasi-Monte Carlo Financial Simulation

Cited by 41 publications

References 8 publications

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

Programming framework for clusters with heterogeneous accelerators

pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

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