High-Performance RSD Poly-Si TFTs With a New ONO Gate Dielectric

Abstract

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger BD , and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm 2 V s, and an on/off current ratio exceeding 10 8 . Index Terms-Gate dielectric, N 2 O-plasma oxynitride, oxide-nitride-oxide (ONO), raised source/drain (RSD), thin-film transistors (TFTs).

Polarity-Dependent Device Degradation in SONOS Transistors Due to Gate Conduction Under Nonvolatile Memory Operations

“…However, it is still necessary to demonstrate good reliability on the part of SONOS devices before the ONO gate structure can confidently replace the traditional tunnel oxide gate dielectric structure. So far, many efforts have been aimed mainly at improving the time-dependent dielectric breakdown (TDDB) characteristics [8]- [10] for gate dielectric layers. However, the reliability concerns of dielectric breakdown have become less critical in recent memory device technology because there has been a dramatic increase in charge-to-breakdown Q BD as the thickness of the gate oxide becomes less than 3.2 nm of the mean-free path of the electrons in the oxide [6].…”

Improving Yield and Performance in ZnO Thin-Film Transistors Made Using Selective Area Deposition

“…In capacitors and TFTs, defects in the insulating layer can allow short-circuits between conductive elements that can be catastrophic for individual devices as well as the circuits containing them. Approaches to forming high-quality dielectric layers typically fall into one of two categories: a single thick layer of a single material or multiple layers of different material types. − In the case of bottom gate devices that use a single-layer dielectric, large thicknesses (>100 nm) are often used to ensure high device yield . In general, however, thick dielectrics are undesirable because of the longer deposition times, and furthermore the resulting devices require a higher operating voltage.…”

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

“…The JL-planar device serves as the control, and the channel dimensions are 15-nm high × 0.95-µm wide. The silicon nitride that is used as a gate insulator reduces the equivalent oxide thickness, achieving a low leakage current and a steep SS[9].Fig. 1(c)shows TEM images along the BB direction in a 70-nm-wide NW.…”