High performance test generation for accurate defect models in CMOS gate array technology

Sucar, Hector R.; Chandra, S.J.; Wharton, D.J.

doi:10.1109/iccad.1989.76928

Cited by 10 publications

(2 citation statements)

References 2 publications

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“…A comprehensive macrocell-based transistor-level fault model was used to evaluate fault coverage [13]. The fault model includes open and shorted transistor faults as well as classical stuck-at faults.…”

Section: Resultsmentioning

confidence: 99%

“…The novel BIST method proposed in this paper extends the Crosscheck grid based embedded test solution [13], [14] to perform a full circuit self-test for synchronous circuits. An on-chp global LFSR is used in conjunction with a new boundary-test structure and a test grid that provides massive, observability of circuit nodes and enables all storage elements to be accessed.…”

Section: O Introductionmentioning

confidence: 99%

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A global BIST methodology

Gheewala¹,

Sucar²,

Varma³

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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This paper presents a BIST methodology for CMOSgate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete serf-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes afforded by an embedded grid allows high fault coverage of both stuck-at and manufacturing defects, such as shorts and opens, to be achieved.

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Section: Resultsmentioning

confidence: 99%

Section: O Introductionmentioning

confidence: 99%

A global BIST methodology

Gheewala¹,

Sucar²,

Varma³

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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Comprehensive structural testing of ASIC macrocells, a comparative analysis

Sucar¹

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

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High performance CMOS array with an embedded test structure

Pierce¹,

Lipp²,

Chan³

et al.

IEEE Proceedings of the Custom Integrated Circuits Conference

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An LSI Logic Compacted ArrayTM containing the CrossCheckw embedded test structure has been developed. The embedded test structure provides massive observability and transistor-level fault modeling while incumng no performance penalty and only a modest area penalty. IntroductionThe problem of test pattern generation for VLSI devices is a major obstacle confronting designers of integrated circuits'. This problem has developed due to improvements in processing technology that permit the fabrication of larger devices. These larger devices have significantly fewer input/output pads per gate than previous devices and are therefore more difficult to test. The test pattern generation problem is even more acute in the case of application specific integrated circuits (ASICs). With ASICs, only the ASIC manufacturer and the particular ASIC user contribute to the testing of the device. In the case of standard parts, the standard part manufacturer and the entire community of customers using that standard part contribute to the testing of that device.Design debug is a second problem confronting IC designers. Improvements in processing technology have resulted in two and three layers of f i e pitch metalization which is no longer conducive to mechanical probing. The altemative of using electron-beam machines is very expensive.A third problem confronting ASIC manufacturers is diagnostics. Processing technology is more complex and involves many more operations than before, giving rise to a greater number of possible failure mechanisms. The stuck-at fault model and current testability techniques do not provide manufacturers with the tools necessary to locate and diagnose manufacturing failures2.This paper describes the implementation of an innovative test and diagnostic solution called Crosscheck that addresses the problems of test pattern generation, design debug and manufacturing diagnostics. The paper begins by giving an overview of Crosscheck, goes on to describe the design considerations during the incorporation of Crosscheck into an LSI Logic Compacted Arraf, and concludes with calculated and measured results.

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High performance test generation for accurate defect models in CMOS gate array technology

Cited by 10 publications

References 2 publications

A global BIST methodology

A global BIST methodology

Comprehensive structural testing of ASIC macrocells, a comparative analysis

High performance CMOS array with an embedded test structure

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