High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

El-Nozahi, Mohamed; Amer, Mohamed A.; Rodríguez‐Torres, Janet; Entesari, Kamran; Sánchez-Sinencio, E.

doi:10.1109/jssc.2009.2039685

Cited by 229 publications

(104 citation statements)

References 6 publications

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“…According to the Table II, the proposed circuit has a better transient performance than [14,15], and has a slightly bigger undershoot than [13] for the difference in load.…”

Section: Simulation Results and Evaluationmentioning

confidence: 97%

A single-event transient hardened LDO regulator with built-in filter

Zhang

Ding

Liu

et al. 2015

IEICE Electron. Express

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A single-event transient (SET) hardened LDO using novel structure is proposed to enhance the single-event effect tolerance. The novel LDO with built-in filter can mitigate the response of the sensitive nodes of circuit. If the SET pulse current flows through the sensitive nodes, the maximum variation of the output voltage is only 15.5 mV. In addition, the transient performance is slightly dropped back as a tradeoff for the built-in filter. When the workload changes transiently between 100 µA and 100 mA in 100 ns, the undershoot is 28.4 mV and the overshoot is nearly 20 mV with imperceptible peak.

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“…According to the Table II, the proposed circuit has a better transient performance than [14,15], and has a slightly bigger undershoot than [13] for the difference in load.…”

Section: Simulation Results and Evaluationmentioning

confidence: 97%

A single-event transient hardened LDO regulator with built-in filter

Zhang

Ding

Liu

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In [6], the ripple on the external supply line is coupled to the gate of the power transistor using a feed-forward amplifier which equalizes the phase delay of the compensating signal path with that of the main path of the power supply noise coupling. However, the feedforward amplifier cannot perfectly equalize the phase delay at all frequencies and operation conditions, which limits the improvement of PSR.…”

Section: Previous Techniques For Improved Power Supply Rejectionmentioning

confidence: 99%

Low Drop-Out (LDO) Voltage Regulator with Improved Power Supply Rejection

Jang

Roh

Moon

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-µm standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-µA.

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“…These days, the high power-supply rejection (PSR) of LDOs over a wide range of frequencies has become more important due to recent technological advancements, which have led to development of high-frequency operating integrated communication devices [1,2,3,4]. However, the PSR performance of the conventional LDOs degrades after the dominant pole frequency of error amplifier [5]. Several advanced techniques have been developed in past to increase the PSR at high frequencies, including a replica pass transistor technique [3], which improves PSR by making the gate voltage effectively track the supply ripples, and a feed-forward ripple cancellation technique [5], which employs a feed-forward path that replicates the supply ripples at the gate of the power transistor to enhance the PSR by making power transistor overdrive voltage ripple free.…”

Section: Introductionmentioning

confidence: 99%

“…However, the PSR performance of the conventional LDOs degrades after the dominant pole frequency of error amplifier [5]. Several advanced techniques have been developed in past to increase the PSR at high frequencies, including a replica pass transistor technique [3], which improves PSR by making the gate voltage effectively track the supply ripples, and a feed-forward ripple cancellation technique [5], which employs a feed-forward path that replicates the supply ripples at the gate of the power transistor to enhance the PSR by making power transistor overdrive voltage ripple free. This paper presents an LDO with high PSR.…”

Section: Introductionmentioning

confidence: 99%