High-Q magnetic inductors for high efficiency on-chip power conversion

Design, Modeling, and Analysis of a 3-D Spiral Inductor With Magnetic Thin-Films for PwrSoC/PwrSiP DC-DC Converters

“…The first approach leads to increased cost as well as process complexity [32]. Also, it involves displacement eddy current loss [33]. The second approach degrades the power handling capacity of the film [34].…”

“…Since this work focuses on small-signal characterization, anomalous loss, which appears at large ac currents, is not taken into account. The losses that need to be considered in the 3-D spiral inductor with magnetic thinfilms are winding loss, eddy current loss, and hysteresis loss; the resistances corresponding to these losses are represented by the winding resistance R w,ac [see (33)], eddy current resistance R e , and hysteresis resistance R h , respectively. The total resistance, R ac , which is known as small-signal resistance, is given by the following equation:…”

A Silicon-Embedded Inductor Surrounded by Porous Silicon for Improved Quality Factor

“…[1][2][3] While in-package SVRs have come into commercial use in the past years, [4][5][6] on-chip SVRs are still in the research phase partly due to the unsatisfactory size-efficiency tradeoffs of currently available on-chip power inductors. [7][8][9][10][11][12][13][14][15][16][17] In SVRs, the power inductor loss is composed of the dc loss which is proportional to the dc resistance (R DC ), and the ac loss which is proportional to (f.L.Q) −1 , where f, L, and Q are the operating frequency, the inductance, and the quality factor of the inductor, respectively. 14 Therefore, thick magnetic cores and thick metal coils are highly preferred for on-chip power inductors to increase L and reduce R DC , respectively.…”

“…Compared to fabricating on-chip power inductors above the silicon substrate, embedding onchip power inductors inside the silicon substrate allows much thicker magnetic cores and metal coils to be achieved. [7][8][9][10][11][12][13] However, these embedded inductors suffer from more significant substrate effects which have negative impacts on f and Q. Previously, porous silicon (PS) technology has been used to suppress the substrate effect for on-chip radio frequency (RF) planar inductors.…”