High quality Ge on Si by epitaxial necking

Langdo, T. A.; Leitz, Christopher; Currie, M. T.; Fitzgerald, Eugene A.; Lochtefeld, A.; Antoniadis, D.A.

doi:10.1063/1.126754

Cited by 210 publications

(137 citation statements)

References 21 publications

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“…8 Another approach is to deposit Ge directly on Si substrate and then introduce annealing step during and/or after the Ge growth to reduce the TDD. [9][10][11][12][13][14][15] However, this approach results in a much higher TDD of >10 7 cm −2 (Refs. [16][17][18] and severe Si/Ge inter-mixing at the in growth interface.…”

Section: 6mentioning

confidence: 99%

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

et al. 2015

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A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

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Section: 6mentioning

confidence: 99%

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

et al. 2015

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“…It has been shown that the high aspect ratio of the STI trench can be used to trap the defects at the bottom of the trench and the STI sidewalls. 2,[16][17][18][19] In this case, a single SiGe layer is used as virtual substrate. This aspect ratio trapping typically works well perpendicular to the trench, but along the trench innovations in epitaxial growth are needed to reduce the number of defects.…”

mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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“…Previous reports have demonstrated that the defect necking effect is limited to trenches with aspect ratio (depth to width) greater than 2 [7,9,10]. pMOS device performance boost on Ge selectively grown in STI trenches has been demonstrated recently [11].…”

Section: Introductionmentioning

confidence: 99%

“…One approach to integrate these materials on Si substrates is SAG in shallow trench isolated (STI) structures [5,6]. Using this approach, it should be possible to obtain extended defect free areas by the so-called defect necking effect [7]. This would enable an alternative route for making III-V channel nMOS devices.…”

Section: Introductionmentioning

confidence: 99%

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

Wang

Leys

Nguyen

et al. 2011

Journal of Crystal Growth

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In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 61 miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [ 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [ 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2.

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High quality Ge on Si by epitaxial necking

Cited by 210 publications

References 21 publications

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

Processing Technologies for Advanced Ge Devices

Growth of high quality InP layers in STI trenches on miscut Si (001) substrates

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