High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures

Abstract

SE'LF-ALIGNED LDD and INTEGRATIONA simple self-aligned LDD structure is utilized in gate-inverted TFYs. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16Mbit SRAM' s or beyond. We will report on fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35pzxO.35prn devices and their aging and temperature performance; a high ZON/IOW ratio of 1 . 2~1 0~ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of ION; and considerations of device scaling and process margins.