A 512-bit EEPROM IP was designed by using just logic process based devices. To limit the voltages of the devices within 5.5 V, EEPROM core circuits, control gate (CG) and tunnel gate (TG) driving circuits, DC-DC converters: positive pumping voltage (V PP =4.75 V), negative pumping voltage (V NN =−4.75 V), and V NNL (=V NN /2) generation circuit were proposed. In addition, switching powers CG high voltage (CG_HV), CG low voltage (CG_LV), TG high voltage (TG_HV), TG low voltage (TG_LV), V NNL_CG and V NNL_TG switching circuit were supplied for the CG and TG driving circuit. Furthermore, a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed. To reduce a power consumption of EEPROM in the write mode, the reference voltages V REF_VPP for V PP and V REE_VNN for V NN were used by dividing V DD (1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators. A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed. The result shows that the power dissipation is 0.34 µW in the read mode, 13.76 µW in the program mode, and 13.66 µW in the erase mode.