High-Speed AES Encryptor With Efficient Merging Techniques

Hammad, Issam; El‐Sankary, Kamal; El-Masry, E.I.

doi:10.1109/les.2010.2052401

Cited by 58 publications

(16 citation statements)

References 5 publications

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“…When compared with 8-bit architectures in terms of maximum frequency, only [21] (when optimized for speed) has a greater maximum frequency than both our implementations, which can be attributed to the differences in design. Furthermore, when compared to 128-bit architectures, [9], [10] and [18] have a higher maximum frequency owing to the fact that [9], [10] and [18] employ an optimized unrolled architecture, multi-staged pipeline architecture and modified architectures of ByteSubstitution and MixColumn operation respectively.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…ByteSubstitution Unit 20.5% (main method))) by mapping the masking values of SBox and MixColumns, along with all intermediate operations, from GF (2 8 ) to (2 4 ) and achieves a high throughput of 40.9 Gbits/s. Unlike most architectures, Hammad et al achieves a 37% improvement in throughput by utilizing a new efficient architecture for AES encryptor by employing an Integrated Box (I-Box) and composite field arithmetic approach [10]. Jing et al [13] modifies MixColumns by proposing three different polynomials for the operation, which results in increase in variety of AES algorithms.…”

Section: Related Workmentioning

confidence: 99%

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FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

Chawla

Goel

2015

2015 Annual IEEE India Conference (INDICON)

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As network technology advances, information security issues increase the need for developing low-area and lowpower high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations through which the data is iterated for ten rounds, which results in substantial reduction in terms of area and power consumption. We have proposed a new architecture for ByteSubstitution and AddRoundKey operations by employing high order masking and a different key expansion algorithm respectively, hence making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks. Moreover, we have also utilized a new architecture for ShiftRows operation for further minimizing the area on chip. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies-Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 200.32 MHz with a throughput of 160.26 Mbps, whereas, with area explore strategy, the proposed architecture utilized 662 slices, 796 LUTs and 0.303 Watt in power.

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Section: Results and Comparisonsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

Chawla

Goel

2015

2015 Annual IEEE India Conference (INDICON)

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“…The RotWord function performs a cyclic permutation on input word gives cyclic right shifted 4 bytes output word. Rcon is array of bytes in a word having fixed logical value having size of 128 bit [2]. A 128 bit Key register is fixed signal used to temporal storage of cipher key computed for each round of operation.…”

Section: Key Expansionmentioning

confidence: 99%

HARDWARE IMPLEMENTATION OF AES ENCRYPTION AND DECRYPTION FOR LOW AREA & POWER CONSUMPTION

Khose¹

2014

IJRET

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An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.

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“…In cryptography, AES is called as Rijndael Encryption algorithm that is capable of protecting sensitive information. [1][2][3][4] 2. AES FRAME WORK Table 1 shows the structure of Rijndael Algorithm adopted by AES. AES uses the data block of 128 bits and Cipher key of 128, 192 or 256.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Advanced Encryption Standard on FPGA

Namdeo¹,

Nautiyal²

2016

IJCA

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The Advanced Encryption Standard is the data security standard referred to as Federal Information Processing Standard 197 (FIPS 197) acquired worldwide by several private and public sectors for protective needs of data storage and secure data application from mobile consumer products to high end user. Most of the AES implementation for reconfigurable devices however based on the configurable logic such as flip-flops and lookup tables. In this paper, all the three modules i.e. AES -128, AES -192 and AES -256 are implemented on Spartan 3 XC3S1000L speed grade -4 FPGA. All the three modules are implemented with four techniques namely, sequential 3 Stage, sequential 2 stage, pipelined and combinational and then a performance of the three techniques is evaluated. At last a combined AES supporting all the three AES types is also implemented using combinational technique. It is observed from the implementations that sequential 2 stage technique is most area efficient technique, whereas pipelined technique is most time efficient technique.

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High-Speed AES Encryptor With Efficient Merging Techniques

Cited by 58 publications

References 5 publications

FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

HARDWARE IMPLEMENTATION OF AES ENCRYPTION AND DECRYPTION FOR LOW AREA & POWER CONSUMPTION

Performance Analysis of Advanced Encryption Standard on FPGA

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