High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder

Shrestha, Rahul; Sahoo, Abhijit

doi:10.1109/tcsii.2018.2877140

Cited by 15 publications

(11 citation statements)

References 11 publications

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“…As for the decoder with 20 cores, it is implemented with D input = 12 and D list = 1 to improve the throughput for the applications that only need to work at a high SNR regime. They both have 512 PEs and adopt the design proposed in [39] to improve the hardware efficiency. Compared with the decoder N core = 18, the critical path delay of the decoder with N core = 20 is longer, since its issue management needs more operations to prepare the unprocessed LLRs.…”

Section: Implementation Results Of the Proposed Architecturementioning

confidence: 99%

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

Wang

Zhang

et al. 2020

IEEE Access

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As the first kind of capacity-achieving forward error correction (FEC) codes, polar codes have attracted much research interest recently. Compared with traditional FEC codes, polar codes show better error correction performance when successive cancellation list (SCL) decoding with cyclic redundancy check is adopted. However, its serial decoding nature and high complexity of list management lead to its low throughput. Though the adaptive SCL decoding and hybrid decoding can improve the throughput, it comes at cost of implementation area. In this paper, we propose a pipelined hybrid decoding procedure and the corresponding hardware architecture to improve the area efficiency. In our design, the idle decoding cores are employed for successive cancellation (SC) decoding when SCL decoding is not working. The SCL decoding will be activated when the SC decoding fails. Different decoding cores work according to their own operation sequences and share one common processing array to improve the utilization ratio of processing elements. Constant receiving interval is supported with the design of input buffer to store all received codewords. A software platform is established to optimize the design parameters for each module of decoder. Moreover, the corresponding architecture is implemented using 65nm technology. Experimental results show that the proposed decoder can achieve a similar error correction performance with the SCL decoding with list size 16. Compared to the state-of-the-art available hybrid decoder, our proposed pipelined hybrid decoder is 3.07× more area efficient.

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Section: Implementation Results Of the Proposed Architecturementioning

confidence: 99%

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

Wang

Zhang

et al. 2020

IEEE Access

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“…Cross-layer calculation for LLRs requires multilevel serial (PEs) structure and memory rearrangement. The PE units use the low-latency architecture proposed in [25]. Fig.…”

Section: Cross-layer Strategy Based On Memory Rearrangementmentioning

confidence: 99%

“…Polar codes have drew signification attention due to the fact that they have low complexity successive-cancellation (SC) decoding algorithm and achieve the capacity of binary input memory-less symmetric-channels (BMC) [1]. However, the serial nature of SC lends to high latency and low throughput when implemented on hardware [2,3,5,25]. In order to address this issue, simplified SC (SSC), Fast-SSC, SSC with maximum-likelihood decoding (ML-SSC) and belief propagation (BP) algorithm were proposed in [7,8,9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

An implementation of fast polar codes decoder with reducing internal memory and supporting flexible code rate

Luo

Guan²,

Liang³

et al. 2022

IEICE Electron. Express

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This letter proposes a fast simplified successive-cancellation (FSSC) polar decoder architecture, supporting any code rate. With the parameter M, which is the maximum limit length of a special polar node, the authors present a novel scheme for online identification of special node in a polar code. In addition, under the parameter M, the proposed decoder has a well optimized architecture to reduce area, power and energy consumption, that due to require less internal memory using cross-layer calculation and less hardware resources for special node without pipeline technology. Synthesis and post-layout simulate results, based in TSMC 65nm CMOS technology, show that the consumption of hardware resources is reduced by 25%. The architecture and circuit techniques reduce the power to 54.9mW for an energy efficiency of 77.22 pJ/b.

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“…Shao et al, [2] Channel coding may be viewed as the bestinformed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference and fading. R. Shrestha et al, [4] This brief presents an algorithm for the processing element (PE) of polar decoder based on 2's complement representation of logarithmic likelihood ratios. It simplifies computation and alleviates critical path delay of PE.…”

Section: Literature Surveymentioning

confidence: 99%

Polar Code: An Advanced Encoding And Decoding Architecture For Next Generation 5G Applications

Maltiyar¹,

Malviya²

2019

IJRITCC

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Polar Codes become a new channel coding, which will be common to apply for next-generation wireless communication systems. Polar codes, introduced by Arikan, achieves the capacity of symmetric channels with “low encoding and decoding complexity” for a large class of underlying channels. Recently, polar code has become the most favorable error correcting code in the viewpoint of information theory due to its property of channel achieving capacity. Polar code achieves the capacity of the class of symmetric binary memory less channels. In this paper review of polar code, an advanced encoding and decoding architecture for next generation applications.

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High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder

Cited by 15 publications

References 11 publications

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

An implementation of fast polar codes decoder with reducing internal memory and supporting flexible code rate

Polar Code: An Advanced Encoding And Decoding Architecture For Next Generation 5G Applications

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