Because they were used for decades to present visual stimuli in psychophysical and psychophysiological studies, cathode ray tubes (CRTs) used to be the gold standard for stimulus presentation in vision research. Recently, as CRTs have become increasingly rare in the market, researchers have started using various types of liquid-crystal display (LCD) monitors as a replacement for CRTs. However, LCDs are typically not cost-effective when used in vision research and often cannot reach the full capacity of a high refresh rate. In this study we measured the temporal and spatial characteristics of a consumer-grade LCD, and the results suggested that a consumer-grade LCD can successfully meet all the technical demands in vision research. The tested LCD, working in a flash style like that of CRTs, demonstrated perfect consistency for initial latencies across locations, yet showed poor spatial uniformity and sluggishness in reaching the requested luminance within the first frame. After these drawbacks were addressed through software corrections, the candidate monitor showed performance comparable or superior to that of CRTs in terms of both spatial and temporal homogeneity. The proposed solution can be used as a replacement for CRTs in vision research.

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As the first kind of capacity-achieving forward error correction (FEC) codes, polar codes have attracted much research interest recently. Compared with traditional FEC codes, polar codes show better error correction performance when successive cancellation list (SCL) decoding with cyclic redundancy check is adopted. However, its serial decoding nature and high complexity of list management lead to its low throughput. Though the adaptive SCL decoding and hybrid decoding can improve the throughput, it comes at cost of implementation area. In this paper, we propose a pipelined hybrid decoding procedure and the corresponding hardware architecture to improve the area efficiency. In our design, the idle decoding cores are employed for successive cancellation (SC) decoding when SCL decoding is not working. The SCL decoding will be activated when the SC decoding fails. Different decoding cores work according to their own operation sequences and share one common processing array to improve the utilization ratio of processing elements. Constant receiving interval is supported with the design of input buffer to store all received codewords. A software platform is established to optimize the design parameters for each module of decoder. Moreover, the corresponding architecture is implemented using 65nm technology. Experimental results show that the proposed decoder can achieve a similar error correction performance with the SCL decoding with list size 16. Compared to the state-of-the-art available hybrid decoder, our proposed pipelined hybrid decoder is 3.07× more area efficient.

To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle scheme to reuse the memory space where the data have been deleted. In our work, the length of the linked-list is parameterized and can be reconfigured. The structure is mapped onto an FPGA chip. Experimental results show that our proposal works functionally well. Only few hardware resources are used and it consumes pretty low power. According to the length of the list, clock speed from 100MHz up to 200MHz is achieved. Compared with the software linkedlist structure in PC, our proposal in FPGA achieves 170.4 times of speedup in average. Our design has been utilized into people tracking system successfully.

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