High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme

Kwon, Chang-Ki; Rho, Kwangmyoung; Lee, Kwyro

doi:10.1109/icvc.1999.820940

Cited by 4 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Current-mode sensing [7]- [11], for instance, decreases the wire delay by a factor of three and increases the bandwidth by the same factor. The equalization techniques in [7], [10]- [12], referred to as dynamic overdriving or pre-emphasis equalization, also both decrease wire delay and increase the achievable data rate. However, the downside to most of these techniques is a significant increase in power consumption (both static and dynamic power).…”

mentioning

confidence: 99%

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Mensink¹,

Schinkel²,

Klumperink

et al. 2010

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.

show abstract

mentioning

confidence: 99%