High Speed Current-mode Signaling Circuits for On-Chip Interconnects

Katoch, A.; Veendrick, H. J. M.; Seevinck, E.

doi:10.1109/iscas.2005.1465542

Cited by 34 publications

(41 citation statements)

References 6 publications

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“…Current-mode sensing [7]- [11], for instance, decreases the wire delay by a factor of three and increases the bandwidth by the same factor. The equalization techniques in [7], [10]- [12], referred to as dynamic overdriving or pre-emphasis equalization, also both decrease wire delay and increase the achievable data rate. However, the downside to most of these techniques is a significant increase in power consumption (both static and dynamic power).…”

mentioning

confidence: 99%

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Mensink¹,

Schinkel²,

Klumperink

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.

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mentioning

confidence: 99%

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

Mensink¹,

Schinkel²,

Klumperink

et al. 2010

IEEE J. Solid-State Circuits

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“…Other researchers have used a dynamic over-driving Tx with a strong and weak driver alongside a low-gain inverter amp Rx and a controlled current source that addresses the previous V CM problem [2]. However, this scheme results in rise-and fall-time mismatch at the output [6] which can be problematic in CDNs.…”

Section: Overview Of Existing CM Signaling Schemesmentioning

confidence: 99%

“…The pulsed current Tx in Figure 3(a) is similar to previous Tx circuits [2], [6], but we have used a NAND-NOR design. The NAND gate uses the CLK signal and a delayed inverted CLK signal, clkb, as inputs to generate a small negative pulse to briefly turn on M1.…”

Section: B Current-mode Transmitter and Distributionmentioning

confidence: 99%

“…Technology scaling reduces transistor and local interconnect delay while increasing global interconnect delay [2]. Moreover, conventional CDN structures are becoming increasingly difficult for multi-GHz ICs because skew, jitter, and variability are often proportional to large latencies [3].…”

Section: Introductionmentioning

confidence: 99%

“…Low-swing and current-mode signaling, however, are highly attractive solutions to help address the interconnect power and variability problems [1], [2], [5], [6]. Static power is typically more significant than dynamic power in CM signaling.…”

Section: Introductionmentioning

confidence: 99%

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Current-mode clock distribution

Islam¹,

Guthaus²

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flipflop (CMPFF) using a representative 45nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.

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