High-speed architectures for Reed-Solomon decoders

Sarwate, D.V.; Shanbhag, Naresh R.

doi:10.1109/92.953498

Cited by 268 publications

(153 citation statements)

References 13 publications

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“…In order not to have to do this costly calculation, many authors have come up with modified versions of the algorithm, e.g. [20][21][22]. However, these are all time-memory tradeoffs of the original inversionless BM algorithm by Burton [5], which we prefer due to its lower storage requirements.…”

Section: Bch Decodingmentioning

confidence: 99%

“…Most BCH decoders are designed with a focus on throughput and use systolic array designs, e.g. [19,20,22]. Aiming for a size-optimized implementation, we propose a serialized, minimalistic coprocessor design with a 10-bit application-specific instruction set and limited conditional execution support.…”

Section: Syndrome Generation and Error Decoding For C Rep And C Bchmentioning

confidence: 99%

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PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

Maes

Herrewege

Verbauwhede

2012

Cryptographic Hardware and Embedded Systems – CHES 2012

211

216

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Abstract. We present PUFKY: a practical and modular design for a cryptographic key generator based on a Physically Unclonable Function (PUF). A fully functional reference implementation is developed and successfully evaluated on a substantial set of FPGA devices. It uses a highly optimized ring oscillator PUF (ROPUF) design, producing responses with up to 99% entropy. A very high key reliability is guaranteed by a syndrome construction secure sketch using an efficient and extremely low-overhead BCH decoder. This first complete implementation of a PUF-based key generator, including a PUF, a BCH decoder and a cryptographic entropy accumulator, utilizes merely 17% (1162 slices) of the available resources on a low-end FPGA, of which 82% are occupied by the ROPUF and only 18% by the key generation logic. PUFKY is able to produce a cryptographically secure 128-bit key with a failure rate < 10 −9 in 5.62 ms. The design's modularity allows for rapid and scalable adaptations for other PUF implementations or for alternative key requirements. The presented PUFKY core is immediately deployable in an embedded system, e.g. by connecting it to an embedded microcontroller through a convenient bus interface.

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Section: Bch Decodingmentioning

confidence: 99%

Section: Syndrome Generation and Error Decoding For C Rep And C Bchmentioning

confidence: 99%

PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

Maes

Herrewege

Verbauwhede

2012

Cryptographic Hardware and Embedded Systems – CHES 2012

211

216

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“…Orthogonal frequency-division multiplexing (OFDM) [10] is a method of digital modulation in which a signal is split into several narrowband channels at different frequencies. OFDM modulator receives the data with parity.…”

Section: Ofdm Modulatormentioning

confidence: 99%

RS and OFDM Methods Over Encrypted and Data Embedded Video Streams

2016

IJSR

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Data hiding techniques are usually used in image processing. It is used to embed a secret message into a image for ensuring privacy. Data hiding can also be applied to videos. So the confidentiality of the image, video and embedded data is maintained. Sometimes digital video needs to be processed in an encrypted format to maintain security and privacy. For the purpose of content notation and/or tampering detection it is necessary to perform data hiding in these encrypted videos. There exist different techniques for hiding private data in videos. Several data hiding techniques in videos have been proposed. The data is embedded by using data hiding algorithm. This method preserves the exact data and video quality. There are some challenges while transmitting an encrypted video with hidden data from a sender to a receiver. At the time of transmission there is a chance of occurrence of errors in the content of video due to the presence of noise and by some other factors. Hence introduced a Reed Soloman error detection and correction method, which detect and correct the error. To improve the data rate through the channel an OFDM (Orthogonal Frequency Division Multiplexing) method is also proposed. These methods provide better efficiency, accuracy and performance.

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“…Compared to the architecture derived based on the ME algorithm, the BM architecture is conventionally thought of as being irregular and having a longer critical path delay, although it uses simpler computations to find the error locator polynomial. Criticisms of the irregular architecture and longer delay of the BM algorithm have recently subsided due to the development of the reformulated inversionless BM (RiBM) architecture [4]. For a t-error-correcting RS code, the RiBM architecture is made up of 3t + 1 identical basic cells with a critical path delay of T mult +T add , where T mult and T add denote the delays of the finite-field multiplier (FFM) and adder, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…The key equation is generally solved by employing the Berlekamp-Massey (BM) algorithm [2]- [4], [18] or the modified Euclidean (ME) algorithm [5]- [14]. Compared to the architecture derived based on the ME algorithm, the BM architecture is conventionally thought of as being irregular and having a longer critical path delay, although it uses simpler computations to find the error locator polynomial.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

Shieh

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for ReedSolomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 μm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.

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High-speed architectures for Reed-Solomon decoders

Cited by 268 publications

References 13 publications

PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

RS and OFDM Methods Over Encrypted and Data Embedded Video Streams

High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

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