High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

Abstract

SUMMARYThis paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for ReedSolomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 μm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.

Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems

“…Although the designs in [3], [4], and [6] have higher throughput rates than that of the proposed decoder, they have much higher hardware cost because they use pipelined multipliers to reduce the critical path delay. From Table 3, the proposed RS decoder with the FME architecture can work at a higher speed and has lower hardware requirements than those of our pervious design in [20]. Compared with the design in [6], the proposed design reduces the hardware requirement by about 36 %.…”

“…The decoder can operate at high data rates with a critical path delay of T mult + T ff , where T mult and T ff denote the delays of the finite-field multiplier (FFM) and flip-flop, respectively. To reduce hardware complexity, an efficient polynomial manipulation scheme based on our previous work [20] is presented to remove redundant information in the polynomial representation of the TME algorithm. Applying the boundary cell simplification and folding techniques, the proposed RS(255,239) decoder obtains a 36 % reduction in hardware requirement and has a better area-time complexity compared to those in [6].…”

Low-complexity architecture for Chase soft-decision Reed-Solomon decoding

“…This implies that each test sequence has at most 31 clock cycles for completing the test. To reduce the hardware requirement and increase the hardware utilization, the architecture with a one-iteration saving scheme [8] is applied to construct the KES unit. Figure 3 shows the proposed folded architecture, with its initial values indicated in rectangular boxes inside the processing elements (PEs).…”