High-speed energy-efficient 5:2 compressor

Najafi, Ardalan; Timarchi, Somayeh; Najafi, Atabak

doi:10.1109/mipro.2014.6859537

Cited by 19 publications

(15 citation statements)

References 14 publications

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“…If the propagation delay is rippled for three horizontally cascaded compressors, then three compressors must be considered in the simulation environment. This fact has been presumed for the architectures reported in [9], [10], [12], [13], [14], [18] and [19] (similar as Figure 2). Meanwhile, in the simulation environment, the propagation delay has been measured from the point that the earliest input transition reaches 50% of V dd , to the point where the latest output signal rises to 50% of the V dd voltage.…”

Section: Simulation Resultssupporting

confidence: 76%

“…As described for 6-2 compressor, post-layout simulations using HSPICE for TSMC standard 90nm CMOS technology along with 0.9V power supply have been carried out to measure the delay and power consumption of the proposed 5-2 compressor and redesigned architectures reported in [8], [9], [10], [12], [13], and [14]. Figure 12 illustrates the results for the correct functionality of the proposed structure along with the delay measurement, which depicts the value of 183ps for the delay of the critical path.…”

Section: The 5-2 Compressormentioning

confidence: 99%

“…Also, the measurement result and comparison for power dissipation at the operating frequency of 100MHz demonstrates that the power consumption of the proposed design is about 97µW, which is not the lowest among the presented works. The designs reported in [13] and [14] have the lowest power consumption. However, the lowest PDP belongs to the proposed scheme.…”

Section: The 5-2 Compressormentioning

confidence: 99%

“…At least a latency of 5 XOR logic gates (in gate-level) is expected for this realization where with the help of some optimizations reported in [8], the delay has been reduced to 4 XOR gates. Although there are many structures reported in the literature [8,9,10,11,12,13,14], none of them have been able to reach latencies less than 4 XOR gates. This partially comes down to the lack of deep consideration and investigation of the original truth table for the 5-2 compressor block.…”

Section: Introductionmentioning

confidence: 99%

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CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Rahnamaei

2020

Informacije MIDEM

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In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes.

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Section: Simulation Resultssupporting

confidence: 76%

Section: The 5-2 Compressormentioning

confidence: 99%

Section: The 5-2 Compressormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Rahnamaei

2020

Informacije MIDEM

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“…In addition, a 5-to-2 compressor could be set up using 3-to-2 compressors. It consists of three 3-to-2 compressors (full adders) in series (Chang, Gu, & Zhang, 2004;Najafi, Timarchi, & Najafi, 2014). This architecture has a critical path delay of six XOR gates.…”

Section: Compressor Cellsmentioning

confidence: 99%

Digital counter cell design using carbon nanotube FETs

Bagherizadeh

Moaiyeri

Eshghi

2017

Journal of Applied Research and Technology

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Compressor and counter cells are the basic blocks used to accumulate the partial products in a multiplication process. In this paper, novel high speed and low power carbon nanotube counter cells are suggested. The efficiency of circuits is improved by using carbon nanotube field-effect transistors (CNFETs). The proposed designs are 4-to-3, 5-to-3, 6-to-3, and 7-to-3 counters. Using HSPICE, these proposed designs are simulated at different conditions. Simulation results confirm that the proposed designs are the fastest counters with lowest PDP in different working circumstance.

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Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

Fathi

Ghasemi

Khoei

2022

Circuit Theory & Apps

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A novel ultra‐high‐speed 5‐2 compressor is presented and discussed in this paper. The proposed structure is developed by modifying the truth table focusing on the carry rippling problem. By reducing the number of the states in the truth table and the complexity of the structure, the total delay is reduced while the power and active area are also improved. The proposed compressor is compared with the best recently reported ones where the designed architecture shows 9%–80% improvement in power delay product (PDP). For a better demonstration of the advantages, the proposed structure is placed in the body of a 16 × 16‐bit multiplier and is compared with the other multipliers consisting of the other 5‐2 compressor architectures. The results indicate an improvement equal to 13%. It must also be mentioned that the gate‐level delay calculation is emphasized in this paper, where a precise estimation method is utilized considering the capacitances at the middle‐stage nodes. Based on the calculations, the designed circuit has the minimum gate‐level delay compared to the other related works due to its minimal intermediate connections. For simulating the proposed structure, a standard CMOS 0.18‐μm process along with HSPICE software is used, where the results show a delay of 266.5 ps with a power consumption of 164 μw.

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High-speed energy-efficient 5:2 compressor

Cited by 19 publications

References 14 publications

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Digital counter cell design using carbon nanotube FETs

Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

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