High-Speed Flex-Circuit Chip-to-Chip Interconnects

Braunisch, Henning; Jaussi, James; Mix, J.A.; Trobough, M.B.; Horine, Bryce; Prokofiev, V.; Lu, Daoqiang; Baskaran, Rajashree; Meier, P.C.H.; Han, Dong‐Ho; Mallory, K.; Leddige, Michael

doi:10.1109/tadvp.2007.909451

Cited by 29 publications

(15 citation statements)

References 16 publications

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“…High speed connectors are used to directly connect the package substrate thereby bypassing the conventional socket and motherboard. This can allow 3Â increase in raw bandwidth and the ability to transmit higher data rates over longer distances as compared to FR4 boards [8].…”

Section: Current Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-tochip communication.

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Section: Current Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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Section: Introductionmentioning

confidence: 99%

“…Thus, the link data rate increase cannot only come from circuit design and process improvements. To improve and extend the reach of copper-based interconnects, several improvement have been suggested including highspeed channel design using low-loss dielectric, smooth copper surfaces, improved connectors and packages [3]- [4].The printed circuit boards (PCB) where the longest signal traces commonly found and where the signal is significantly attenuated impose limitation on the supported speed. In order to predict and optimize the performance of high-speed links operating at 50 Gbps and beyond, it is essential to accurately model and characterize the interconnect systems, such as long traces in backplanes.…”

mentioning

confidence: 99%

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

Beyene

Hahm

Secker

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented. IntroductionMemory bandwidth requirements for high performance computing, data centers, servers and storages, driven by internet in general and multi-core memory and processors architectures in particular, are rapidly increasing to meet the performance demands of today's applications [1]-[2]. The high bandwidth necessitates a large increase in the interface data rate and width.The design of high-speed links that operate at data rate exceeding 50 Gbps is necessary to support Terabit backplane systems. In the past, the increase the performance of the input/output (I/O) circuits and the use of more complex equalization, complicated coding and modulation and other signal processing techniques have been able to sustain the growth of data rate. However, the electronic and I/O power consumption significantly increases with increasing the interface speed. Thus, the link data rate increase cannot only come from circuit design and process improvements. To improve and extend the reach of copper-based interconnects, several improvement have been suggested including highspeed channel design using low-loss dielectric, smooth copper surfaces, improved connectors and packages [3]- [4].The printed circuit boards (PCB) where the longest signal traces commonly found and where the signal is significantly attenuated impose limitation on the supported speed. In order to predict and optimize the performance of high-speed links operating at 50 Gbps and beyond, it is essential to accurately model and characterize the interconnect systems, such as long traces in backplanes. The models of interconnects have to be broadband and include high frequency effects that were not critical at lower data rates [5]. For higher data rates, proper identification of the frequency-dependent properties of the

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“…The FPC interconnect has also been used to extend the range of high speed processor to processor links on the same board. [3][4] In this paper, a flexible interconnect was chosen to bypass the traditional memory connector and the electrical problems it posed. It can also avoid the plated through-hole vias if assembled on to the surface layers of the package and PCB.…”

mentioning

confidence: 99%

“…These included both low profile separable connections and permanent lapped connections. [5] The separable connections included conductive elements in elastomer, conductive bump contacts, socket based [4], finepitch single piece connectors, and mating two-piece connectors. The permanent lapped connections included anisotropic conductive adhesives, micro-dispersion solder jointing, solder or conductive adhesives and resistive or ultrasonic welds.…”

mentioning

confidence: 99%

Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth

Kollipara

Yuan

et al. 2008

2008 58th Electronic Components and Technology Conference

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An LCP flex based interconnect that significantly improves the interconnect density and supports data rates in the range of 10 to 16 Gbps is evaluated to enable future high bandwidth module based memory systems without requiring complex equalization techniques. A mating two-piece, lowprofile, high density and small insertion force connector is developed for interfacing the flex to a flip-chip package. The 216 pin connector can support 72 differential pairs in a 6 x 12 array.

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High-Speed Flex-Circuit Chip-to-Chip Interconnects

Cited by 29 publications

References 16 publications

Chip-to-chip interconnect integration technologies

Chip-to-chip interconnect integration technologies

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth

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