High-speed low-power FinFET based domino logic

Rasouli,; Koike,; Banerjee,

doi:10.1109/aspdac.2009.4796583

Cited by 5 publications

(2 citation statements)

References 12 publications

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“…Jafari et al have proven that FinFET is a promising technology for designing robust and power efficient asynchronous circuits [15]. A novel FinFET based domino logic is presented in [16]. Its logic shows higher performance and lower power consumption than standard domino logic, which is beneficial in high fan-in logic.…”

Section: Introductionmentioning

confidence: 99%

Low power adiabatic logic based on FinFETs

Liao

Cui

Liao

et al. 2014

Sci. China Inf. Sci.

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Section: Introductionmentioning

confidence: 99%

Low power adiabatic logic based on FinFETs

Liao

Cui

Liao

et al. 2014

Sci. China Inf. Sci.

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“…In [7], four variants for the same function were designed: conventional shorted-gate (SG) mode, independent-gate (IG) mode with merged parallel transistors driven by independent inputs, low power (LP) mode with a reverse-biased back-gate, and an IG/LP mode that combined the LP and IG modes. The use of an independent-gate voltage keeper to improve the reliability of dynamic logic has also been proposed in [9] and [10]. However, no published work based on FinFETs has extensively explored the possibility of merging series transistors to reduce power and area.…”

Section: Introductionmentioning

confidence: 99%

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Rostami

Mohanram

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-V th independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-V th FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

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Design of energy efficient domino logic circuit using lector technique

Verma

Kumar

et al. 2022

International Journal of Electronics

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High-speed low-power FinFET based domino logic

Cited by 5 publications

References 12 publications

Low power adiabatic logic based on FinFETs

Low power adiabatic logic based on FinFETs

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

Design of energy efficient domino logic circuit using lector technique

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