High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

Raj, Marshal; Lakshminarayanan, G.

doi:10.1109/les.2021.3098017

Cited by 7 publications

(10 citation statements)

References 34 publications

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“…In order to showcase the ability of the proposed designs to be used in different circuits, a 2 × 2 array multiplier and 2 × 2 serial multiplier are realized in this section using the proposed adder. Several multiplier circuits are proposed in QCA [25,[29][30][31][32][33][34][35]. In [25,29], serial multipliers are designed.…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

“…Several multiplier circuits are proposed in QCA [25,[29][30][31][32][33][34][35]. In [25,29], serial multipliers are designed. In [29], a 4-bit serial multiplier with shift registers is designed.…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

“…In [25,29], serial multipliers are designed. In [29], a 4-bit serial multiplier with shift registers is designed. The shift registers are used to store the input and the output.…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

“…In [30,31], array multipliers are designed. In [29,32], serial-parallel multipliers are realized. Square circuits are also realized in QCA [36].…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

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Reliable adder and multipliers in QCA technology

Raj¹,

Lakshminarayanan²

2022

Semicond. Sci. Technol.

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Quantum-dot Cellular Automata (QCA) nanotechnology is an interesting circuit design technology which is based on columbic repulsion and Majority logic. Reliability is a key issue in QCA circuits. In this work, an adder is proposed with better fault tolerance and reduced complexity by combining 3-input majority logic and 5-input majority logic gates. The proposed design is realized by using clock zone approach. Hence, the proposed design deploys only normal cells for its realization. This makes the proposed design less vulnerable to fabrication faults. This is validated by performing extensive fabrication defect analysis. A novel expression to compute the circuit complexity is also proposed. The proposed multipliers consume almost 55% lesser energy compared to the existing designs. The proposed adder is used to realize a reliable array and serial multiplier. The proposed adder can be used in any circuits at the basic elements.

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Section: Reliable Multiplier Designsmentioning

confidence: 99%

Section: Reliable Multiplier Designsmentioning

confidence: 99%

“…In [25,29], serial multipliers are designed. In [29], a 4-bit serial multiplier with shift registers is designed. The shift registers are used to store the input and the output.…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

“…In [30,31], array multipliers are designed. In [29,32], serial-parallel multipliers are realized. Square circuits are also realized in QCA [36].…”

Section: Reliable Multiplier Designsmentioning

confidence: 99%

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Reliable adder and multipliers in QCA technology

Raj¹,

Lakshminarayanan²

2022

Semicond. Sci. Technol.

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“…FIR structure based serialparallel multiplier realized by multilayer crossover method [7]. The serial-parallel multiplier is resourcefully constructed using adders and shift registers and is simulated in QCAPro tool [8]. The N-bit multilayer based QCA adders: ripple-carry adder, Brent-Kung adder, Kogge-Stone, Ladner-Fischer and Han-Carlson adder were designed using optimizing full-adder [9][10].…”

Section: Introductionmentioning

confidence: 99%

A Novel QCA Fine Grained Array Multiplier using Clock Zone Based Crossover

karuppiah,

deivasigamani

2024

Preprint

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The crossover issues in geometric design complexity and alignment accuracy deter the performance of the Quantum-Dot Cellular Automata (QCA) digital logic circuits at nano-scale. The proposed novel Fine Grained Array Multiplier (FGAM) architecture conquers fabrication difficulties and optimizes the clock delay usage. The energy dissipation of Processing Element (PE) using Clock Zone-Based Crossover (CZBCO) is 5.4% lesser compared to PE using coplanar design and 6.6% lesser than PE using multilayer design. The performance of the proposed fine-grained array multiplier is validated by considering design complexity, delay, irreversible power dissipation and wire cost. The QCA cost function of the proposed FGAM has outperformed the multiplier implemented in the literature. Thus, the proposed multiplier significantly achieved high device density, reduction of energy dissipation and overcome fabrication difficulties.

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