High-temperature performance of state-of-the-art triple-gate transistors

Akarvardar, K.; Mercha, A.; Simoen, Eddy; Subramanian, Vaidyanathan; Claeys, Cor; Gentil, P.; Cristoloveanu, S.

doi:10.1016/j.microrel.2006.10.002

Cited by 24 publications

(11 citation statements)

References 14 publications

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“…regimes where influence of series resistance is stronger. Similar trends in G m and I d temperature behavior were previously reported with channel length shortening in both planar [21] and multiple-gate [11,22] advanced devices known to suffer from higher series resistance which can then dominate high current level degradation in place of mobility.…”

Section: Resultssupporting

confidence: 82%

“…FD SOI defined by variation of Fermi potential (¨V T /¨T = ¨φ F /¨T = 1.2 -1 mV/°C for N A =10 15 -10 16 cm -3 ). Similar low values were previously reported for other advanced devices operated under volume inversion conditions [10][11][12]. The reason is that in thin undoped devices, which operate in quasi-volume inversion regime, surface potential at threshold differs significantly from 2φ F [13], and hence above approach is no longer valid.…”

Section: Resultssupporting

confidence: 78%

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High-temperature perspectives of UTB SOI MOSFETs

Kilchytska

Andrieu

Faynot

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

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In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultrathin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses as well as channel doping on the degradation of main device parameters over the temperature range. IntroductionUltra-thin body (UTB) fully-depleted (FD) SOI MOSFETs are widely considered as one of the most promising candidates for ultimate device scaling requested by ITRS thanks to their immunity to short channel effects (SCE) [1][2][3][4][5]. Additionally, employment of ultra thin BOX (i.e. so called UT2B) allows suppression of fringing electric fields through the BOX thus further improving SCE control. Then, simulations predict a reduction of self-heating effects (SHE) in MOSFETs with thin-BOX. Moreover, ultra-thin BOX allows the use of back-gate control schemes. The drawback of UT2B is enhanced coupling through the substrate [6] thus giving additional motivation to the use of ground plane. Electrostatics, scalability and variability issues in UTB MOSFETs as well as their perspectives for low power digital applications are widely discussed in the literature [1][2][3][4][5]. Last years some works assessing their analog features also appeared [7,8]. However, till now no special attention was paid to particularities of UTB SOI MOSFETs in high-temperature range. Understanding of device behavior at high temperatures is important not only from the view point of their possible future application in high-temperature electronics. The ability to predict the high-temperature behavior of advanced devices is of high importance also due to the possible self-heating effect, which leads to the increase of the device temperature (especially strong in short-channel and SOI-like devices) under standard (room temperature) operation conditions. In this work based on experimental and simulations results we discuss the specific features of UTB hightemperature behavior in a temperature range up to 300°C -350°C. Our analysis is focused on the main device parameters, such as threshold voltage, V T , subthreshold slope, S, transconductance maximum, G mmax and drain current, I dnorm. Using 2D physical device simulations we compare devices with different Si film thicknesses, with different channel dopings and different BOX thicknesses typically used in UTB SOI devices. The purpose of such comparison is two-fold: from one side, to assess which device configuration is more favorable for high-temperature range, from another side, to give a first rough insight on variability related issues at higher temperatures. Experimental and simulations detailsUTB SOI MOSFETs with ultra-thin BOX (UT2B) were processed at CEA-LETI on UNIBOND (100) SOI wafers with 10-nm-thick BOX [3]. In the channel region, the Si body was thinned down to about 7 nm. Elevat...

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Section: Resultssupporting

confidence: 82%

Section: Resultssupporting

confidence: 78%

High-temperature perspectives of UTB SOI MOSFETs

Kilchytska

Andrieu

Faynot

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

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“…If available, long channel device data has been included. The off-state leakage current of the dehancement mode FET is significantly lower compared to reported SOIFET, 24 JLFET 8 and FINFET 25 transistors. Furthermore, the simulation results of a DeFET device with 500/250 nm BGL/FGL and 5 nm body thickness are included to demonstrate the potential of future DeFET device generations.…”

Section: Bg / Fg Biasingmentioning

confidence: 59%

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Krauss

Wessely

Schwalke

2015

ECS J. Solid State Sci. Technol.

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In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device. The dominating leakage path for OFF-state currents in today's downscaled MOSFET devices originate from PN-junction and bulk leakage.1,2 These leakage currents increase severely with temperature. SOI technologies can significantly reduce bulk leakage currents. However, junction leakage because of reversed bias PN-junctions is still present in SOI MOSFETs.2 Therefore, our device concept replaces conventional S/D PN-junctions with Schottky barrier contacts in a virtually dopant-free CMOS environment. Many groups have demonstrated the advantages of SBFET devices like low S/D resistance as well as abrupt junctions enabling further scaling and suppression of parasitic bipolar behavior.4,5 Furthermore, JLFET demonstrating high temperature robustness have been reported. [6][7][8] We have combined the advantages of the SBFET and JLFET concepts on SOI in a novel asymmetric dual gate but single channel device. This combination improves the high temperature robustness as reported recently for our SiNW FETs.9,10 For the first time, we have successfully extended this 3D-SiNW concept to planar, non-nanowire device structures.We found that the combination of an ambipolar electrostatic doping back-gate (BG) in addition to an electrically separated current flow control front-gate (FG) in a single device results in a superior on-tooff current ratio and leakage suppression at high temperatures. The BG transistor as a SBFET shows an ambipolar behavior similar to the SBFET reported in.11 On the other hand, the unipolar FG transistor resembles the behavior of a JLFET as reported in Ref. 8. Furthermore, as no conventional impurity doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility or statistic dopant fluctuation and resulting threshold voltage variation following the argumentation of 6 for JLFET devices. In addition, the degree of freedom to instantly select n-and ptype behavior via an ordinary electrical signal of appropriate polarity on the BG allows designing reconfigurable circuits with increased functionality.12 Until now, all ambipolar devices using a separate gate to control the current flow between source and drain involve nanowire structures as, for example, silicon nanowires or carbon nanotubes....

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“…The increase of temperature increased the intrinsic carrier concentration in silicon, which in turn increased the leakage current and a tendency of degrading the ratio of I on /I off (Fig. 16, [26,27]). The carrier mobility increased as the temperature increased, which resulted in increased leakage current with increasing temperature, as shown in Fig.…”

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator ATLAS™ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/ off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

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High-temperature performance of state-of-the-art triple-gate transistors

Cited by 24 publications

References 14 publications

High-temperature perspectives of UTB SOI MOSFETs

High-temperature perspectives of UTB SOI MOSFETs

Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

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