High-Temperature Stability of Lanthanum Silicate Gate Dielectric MIS Devices with Ta and TaN Electrodes

Lichtenwalner, Daniel J.; Jha, Rashmi; Inoue, N.; Chen, Bei; Misra, Veena; Kingon, Angus I.

doi:10.1149/1.2218757

Cited by 11 publications

(12 citation statements)

References 28 publications

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“…LaSiO x /Si interface. We previously reported the lowering of work function on LaSiO x dielectric with Ta or TaN gate electrode (1), which is compared with the present findings (Fig. 6).…”

Section: Resultssupporting

confidence: 87%

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Lee¹,

Lichtenwalner²,

Kingon³

2007

ECS Trans.

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The effective work functions (EWF) of thin transparent conducting oxide (TCO) interlayers, i.e. indium tin oxide (ITO) and indium zinc tin oxide (IZTO), on lanthanum silicate metal-insulatorsemiconductor (MIS) devices were examined. The properties were compared to those obtained using conventional metal electrodes. It was found that the EWF of all metal gates investigated was lowered by ~0.3 -0.4 compared to expected values, due to effects related to the lanthanum silicate dielectric stack. The presence of the TCO electrode layer yielded EWF values ranging from 4.05 to 4.45 eV depending primarily on the annealing condition, regardless of the TCO type. As it is known that ITO can have a work function ~4.75 eV, the presence of the oxide electrode still results in an EWF ~0.3 -0.4 eV below expected values. These results indicate that EWF lowering in lanthanum silicate gate stacks is not strongly dependent on the top interface.

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“…LaSiO x /Si interface. We previously reported the lowering of work function on LaSiO x dielectric with Ta or TaN gate electrode (1), which is compared with the present findings (Fig. 6).…”

Section: Resultssupporting

confidence: 87%

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Lee¹,

Lichtenwalner²,

Kingon³

2007

ECS Trans.

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“…[5][6][7] However, employing such a technique to remove the IL completely for the purpose of improved IPD leakage for flash memories has not yet been investigated. The focus of this study therefore is to investigate the impact of the SiO 2 IL removal by rare-earth scavenging and study its effect on the electrical characteristics of the IPD stack.…”

Section: Technique To Improve Performance Of Al 2 O 3 Interpoly Dielementioning

confidence: 99%

“…To this end, we have used ultrathin layers of La 2 O 3 to scavenge the SiO 2 IL and form silicates. 6,7 A combination of electrical, material, and simulation studies were performed to gain insight into the effectiveness of rare-earth scavenging of SiO 2 layers for application in memory devices.…”

Section: Technique To Improve Performance Of Al 2 O 3 Interpoly Dielementioning

confidence: 99%

Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures

Jayanti

Yang

Lichtenwalner

et al. 2010

Applied Physics Letters

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A technique of scavenging the SiO2 interfacial layer (IL) to improve the electrical performance of Al2O3 as the interpoly dielectric for flash memories has been studied. Scavenging was performed by the reaction of a thin La2O3 layer with the native oxide to form a high-κ lanthanum silicate. Significant improvement in the charge trapping and leakage characteristics were obtained. Transmission electron microscopy analysis was done to corroborate the electrical results. Results show that seven orders of magnitude leakage reduction was achieved by the replacement of the SiO2 IL with a higher-κ dielectric LaSiO at the Si interface.

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“…Effective fixed charge appears to change to negative charge as temperature was elevated up to 1000 C. However, this may be related to reactivity of the Ta electrode at anneal temperatures above 800 C. 41) Since determining the amount of the fixed charge including sign of the charge also suffers from an uncertainty of the work function of the gate electrode, it may not be true that the sign of charge changed. Improvement of interface properties by annealing at high temperature may be due to SiO 2 growth 37) or stress relaxation.…”

Section: Annealing Effect On Interface Propertiesmentioning

confidence: 99%

Analysis of Interface States in LaSi_xO_y Metal–Insulator–Semiconductor Structures

Inoue

Lichtenwalner

Kingon

2007

jjap

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Using a comprehensive model to simulate interface state effects on metal-insulator-semiconductor (MIS) device in capacitance-voltage (C-V) behavior, interface properties of LaSi x O y gate dielectric MIS structures were analyzed. Under low temperature (400 C) processing conditions amenable to low (0.6 nm) equivalent oxide thickness (EOT), LaSiO-based MIS capacitors on n-and p-type substrates have a high density localized interface state. The peak densities of this localized state for MIS devices on n-and p-type substrates are ð2:0 { 2:5Þ Â 10 13 and 2:5 Â 10 12 cm À2 eV À1 , respectively, lying deep in the Si bandgap (within 0.1 eV of midgap). Positive fixed charge density is derived as in the range of 10 13 cm À2 and is found to be distributed close to the interface region. In the case of the p-type MIS capacitor, positive fixed charge and positively charged interface states shift the C-V curve in the negative direction. Interface states in the n-type MOS capacitor capture electrons, compensating for the positive fixed charge and positively charged interface states. Thus less shift of the C-V curve is observed, compared to the p-type case. Interface state and fixed charge densities drastically reduce by raising post annealing temperature, to <10 12 cm À2 eV À1 on n-type Si, but with concurrent EOT increase. Forming gas annealing (FGA) is effective for reducing the localized interface state density, but only when the temperature is 600 C or higher. Results point to a need to minimize defect densities during or immediately after dielectric deposition. The high levels of positive defect states warrant further detailed investigation of the charge trapping characteristics of these dielectrics, as La-containing dielectrics are important for threshold voltage control for metal-oxide-semiconductor field effect transistor (MOSFET) devices.

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High-Temperature Stability of Lanthanum Silicate Gate Dielectric MIS Devices with Ta and TaN Electrodes

Cited by 11 publications

References 28 publications

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures

Analysis of Interface States in LaSi_xO_y Metal–Insulator–Semiconductor Structures

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High-Temperature Stability of Lanthanum Silicate Gate Dielectric MIS Devices with Ta and TaN Electrodes

Cited by 11 publications

References 28 publications

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Investigation of Conducting Oxide and Metal Electrode Work Functions on Lanthanum Silicate High-k Dielectric

Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures

Analysis of Interface States in LaSixOy Metal–Insulator–Semiconductor Structures

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Analysis of Interface States in LaSi_xO_y Metal–Insulator–Semiconductor Structures