High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing

Chen, Zhengyu; Gu, Jie

doi:10.1109/jssc.2020.3021066

Cited by 22 publications

(6 citation statements)

References 25 publications

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“…DTW measures the similarity between two temporal sequences, accommodating variations in speed and length and thereby effectively addressing distortions in the time axis. Despite its strengths, it still operates within the time domain and incurs significant computational overhead, making it less efficient for large-scale datasets [22].…”

Section: Dynamic Time Warping (Dtw)mentioning

confidence: 99%

GT-DTW: Bridging Graph Theory and Dynamic Time Warping for Complex Time Series Analysis

Mahajan

2023

Preprint

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<p>Classification of time series data plays a critical role across various domains, enabling pattern recognition and trend prediction. Traditional methods like Dynamic Time Warping (DTW) have been widely used to measure similarity between time series, but there are challenges related to computational complexity and sensitivity to noise. The conventional DTW approach, with its quadratic time complexity, can be inefficient for large datasets, and some implementations may struggle with noise and local variations. To overcome these limitations, a novel method called Graph-Theoretic Dynamic Time Warping (GT-DTW) is proposed. GT-DTW represents each time series as a graph, applies DTW on the graph representations and calculates the distances between different time series based on these graph representations. This approach provides a robust and computationally efficient method for time series classification, and experimental results show that GT-DTW provides better results when compared with conventional methods on the benchmark datasets from the UCR time series database. GT-DTW also demonstrates enhanced effectiveness in situations where time series share fundamental similarities, yet are affected by intricate transformations, noise, inconsistencies in length, and localized distortions.</p>

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Section: Dynamic Time Warping (Dtw)mentioning

confidence: 99%

GT-DTW: Bridging Graph Theory and Dynamic Time Warping for Complex Time Series Analysis

Mahajan

2023

Preprint

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“…Besides, the weights are transferred from "−1/+1" to "0/1" by formula (6) according to the computation logic map table of the proposed cell. Thus, the partial sum (PSUM) also needs a transform as described in (7), where A count is an accumulation of all input activations.…”

Section: Behavioral Simulationmentioning

confidence: 99%

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

Song

Wang

Guo

et al. 2021

IEEE Trans. Circuits Syst. I

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In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%-98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

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“…By adjusting the accuracy of the digital to time conversion, the calculation engine also enables four modes of acceleration, which to a certain extent alleviates the problem of slow computing caused by the cumulative nature of the time domain delay. In the same year, Chen and Gu [55] designed a time-domain computational gas pedal for the dynamic time-regularization algorithm, a classical algorithm for time series classification problems. To implement the pipeline, they designed a special time domain flip-flop as the time domain memory.…”

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

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High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing

Cited by 22 publications

References 25 publications

GT-DTW: Bridging Graph Theory and Dynamic Time Warping for Complex Time Series Analysis

GT-DTW: Bridging Graph Theory and Dynamic Time Warping for Complex Time Series Analysis

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

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