High throughput non-contact SiP testing

Moore, B.; Sellathamby, C.; Cauvet, Philippe; Fleury, Hervé; Paulson, Molly; Reja, M.M.; Fu, Lin; Bai, B.; Reid, E.; Filanovsky, I.M.; Slupsky, S.

doi:10.1109/test.2007.4437595

Cited by 17 publications

(5 citation statements)

References 12 publications

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“…Depending on the distance between the wafer and the test vehicle, either near-or far-field testing will be suitable for testing. In the same paper, and in [19], it is reported that a complete contactless technique has been implemented and applied to production. However, this technique employs transceivers and antennas in the devices under test, which represents the core of the approach.…”

Section: Related Workmentioning

confidence: 98%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

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State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

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Section: Related Workmentioning

confidence: 98%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

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“…Solutions include contactless test [109] or inserting additional probing pads to non-bottom dies at the cost of increased area [110]. Another concern is whether to perform the test before or after wafer thinning [111].…”

Section: Pre-bond Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…This requires a collaborative effort of probe card makers [34][35][36] and probe station makers alike [37], as it is the sum of the accuracy tolerances that define the overall system accuracy (see Figure 8). Efforts are also spent on contact-less testing [38][39][40], which by definition does not cause any probe damage, but currently still lacks in pitch and density. Until a robust probe technology is available for fine-pitch microbumps, the only solution to enable pre-bond testing is to equip non-bottom dies with additional probe pads, sized such that today's probe technology can handle them.…”

Section: External Test Access: Probe Accessmentioning

confidence: 99%

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D-and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D-and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.

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High throughput non-contact SiP testing

Cited by 17 publications

References 12 publications

Contactless Testing of Circuit Interconnects

Contactless Testing of Circuit Interconnects

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

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