High-Voltage CMOS ESD and the Safe Operating Area

Walker, Andrew; Puchner, H.; Dhanraj, S.P.

doi:10.1109/ted.2009.2022698

Cited by 36 publications

(14 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…8. A similar phenomenon is found in [9], attributed to cumulative soft failure caused by filamentation and contact spiking. For the LDMOS with 7 lm DCGS, the trigger voltage walk-in effect is eliminated.…”

Section: Ldmos For 30 V Hv Esd Protectionsupporting

confidence: 74%

See 1 more Smart Citation

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Han

et al. 2012

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Ldmos For 30 V Hv Esd Protectionsupporting

confidence: 74%

“…In high voltage processes, the LDMOS is known to be very weak during ESD stress related to the base push-out effect [9]. In order to improve its robustness without altering the process conditions, layout optimization was carried out and successfully implemented in an IC product.…”

Section: Ldmos For 30 V Hv Esd Protectionmentioning

confidence: 99%

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Han

et al. 2012

Microelectronics Reliability

View full text Add to dashboard Cite

“…Under output mismatch condition, high power returned to the LDMOS drain, leading to high drain voltage, resulting in strong electric field at the drift region. Then more electron-hole pairs are generated and the hole current may trigger the conduction of NPN transistor, leading to formation of early filament [7,8], which may cause failure of device. To improve robustness, the electric field at drift region near the drain has to be decreased to restrain the formation of electron-hole pairs.…”

Section: Methods and Tcad Simulationmentioning

confidence: 99%

“…Robustness of LDMOS correlated with the inherently presented parasitic bipolar NPN transistor [6], and more body doping was suggested to suppress the turn-on of NPN transistor. The device could fail because of formation of early filament [7,8]; deep implantation drain contact [9] and ESD implantation at drain side [10] were suggested to address the formation of early filament issue. This paper discusses the linearity and robustness together for the first time.…”

Section: Introductionmentioning

confidence: 99%

Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect

Song

2019

Active and Passive Electronic Components

View full text Add to dashboard Cite

This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electronhole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.

show abstract

“…[6,7] An effective method to solve this problem is to use a semiconductor control rectifier-laterally diffused metal oxide semiconductor (SCR-LDMOS); [8] however, its low holding voltage and latch-up immunity are challenging issues for its application. [9] Increasing the holding voltage is an effective way to achieve latch-up immunity of the ESD protection device. [10] Using a stacked device structure can achieve a high holding voltage.…”

Section: Introductionmentioning

confidence: 99%

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

Ma¹,

Qiao²,

Zhang³

2015

Chinese Phys. B

View full text Add to dashboard Cite

A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-µm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

show abstract

High-Voltage CMOS ESD and the Safe Operating Area

Cited by 36 publications

References 21 publications

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

Contact Info

Product

Resources

About