High-Voltage Regrown Nonpolar &lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;${m}$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt;-Plane Vertical p-n Diodes: A Step Toward Future Selective-Area-Doped Power Switches

Monavarian, Morteza; Pickrell, G.; Aragon, Andrew; Stricklin, Isaac; Crawford, Mary H.; Allerman, Andrew A.; Celio, Kimberlee Chiyoko; Léonard, François; Talin, A. Alec; Armstrong, Andrew M.; Feezell, Daniel

doi:10.1109/led.2019.2892345

Cited by 24 publications

(10 citation statements)

References 20 publications

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“…Si accumulation due to exposure to the ambient air is a known problem for compound semiconductors. [ 22,23 ] Due to the high temperature, the Si then diffuses from the surface into the bulk. The C concentration in the AlGaN layer stays constant at 2 × 10 18 cm −3 and is not changed by HTA (Figure 9b).…”

Section: Resultsmentioning

confidence: 99%

High‐Temperature Annealing of AlGaN

Hagedorn

Khan

Netzel

et al. 2020

Physica Status Solidi (a)

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In the past few years, high‐temperature annealing of AlN has become a proven method for providing AlN layers with low dislocation densities. Herein, the example of Al0.77Ga0.23N is used to investigate whether annealing can also improve the material quality of the ternary alloy. A detailed analysis of the influence of annealing temperature on structural and optical material properties is presented. It is found that with increasing annealing temperature, the threading dislocation density can be lowered from an initial value of 6.0 × 109 down to 2.6 × 109 cm−2. Ga depletion at the AlGaN surface and Ga diffusion into the AlN buffer layer are observed. After annealing, the defect luminescence between 3 and 4 eV is increased, accompanied by an increase in the oxygen concentration by about two orders of magnitude. Furthermore, due to annealing optical absorption at 325 nm (3.8 eV) occurs, which increases with increasing annealing temperature. It is assumed that the reason for this decrease in ultraviolet (UV) transmittance is the increasing number of vacancies caused by the removal of group‐III and N atoms from the AlGaN lattice during annealing.

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Section: Resultsmentioning

confidence: 99%

High‐Temperature Annealing of AlGaN

Hagedorn

Khan

Netzel

et al. 2020

Physica Status Solidi (a)

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“…More details on the growth parameters may be found elsewhere. [18] Various surface treatments were then applied on pieces of the drift layer to introduce different impurity types/levels at the sample surface prior to the p-GaN growth. For the first set of experiments, the regrowth interfaces were placed directly at the metallurgical junctions between the n-GaN drift region (n ~ 6×10 16 cm -3 ) and the p-GaN (p ~ 1×10 19 cm -3 ).…”

Section: Experimental Details and Resultsmentioning

confidence: 99%

“…Therefore, the presence of a doping spike associated with an interfacial Si impurity increases the peak electric field within the diode, but may not be directly responsible for early breakdown since previously reported critical electric fields on regrown diodes were above 3.35 MV/cm. [18] Nevertheless, the peak electric field decreases when the delta-doped spike is buried further in the n -GaN compared to the delta-doped diode at the metallurgical junction. The peak electric fields of the delta-doped diodes at 300 nm and 600 nm away from the metallurgical junction were calculated to be ~ 1.2 MV/cm and 1.1…”

Section: Author Manuscriptmentioning

confidence: 99%

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Interfacial Impurities and Their Electronic Signatures in High‐Voltage Regrown Nonpolar m‐Plane GaN Vertical p–n Diodes

Aragon

Monavarian

Stricklin

et al. 2019

Physica Status Solidi (a)

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“…Despite the feasibility of p-GaN trench-filling epitaxy, the presence of n-type interface charges has been widely reported for the p-GaN regrowth on different GaN lattice planes [11]- [14]. The physical origin of this interface charges is often attributed to the impurities (Si, O, C, mainly Si) in the growth chamber or in the environments during the device transfer to the growth chamber [12]- [14]. The donor-type nitrogen vacancies at the etched sidewalls, which have been widely reported in vertical GaN devices [15]- [17], may also contribute to the interface charge.…”

Section: Introductionmentioning

confidence: 99%

Superjunction Power Transistors With Interface Charges: A Case Study for GaN

Xiao

Zhang

et al. 2020

IEEE J. Electron Devices Soc.

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Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds ∼3×10 12 cm −2 , the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.

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High-Voltage Regrown Nonpolar <inline-formula> <tex-math notation="LaTeX">${m}$ </tex-math> </inline-formula>-Plane Vertical p-n Diodes: A Step Toward Future Selective-Area-Doped Power Switches

Cited by 24 publications

References 20 publications

High‐Temperature Annealing of AlGaN

High‐Temperature Annealing of AlGaN

Interfacial Impurities and Their Electronic Signatures in High‐Voltage Regrown Nonpolar m‐Plane GaN Vertical p–n Diodes

Superjunction Power Transistors With Interface Charges: A Case Study for GaN

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