Highly accurate capacitor‐free LDO with sub‐1 V −120 dB PSRR bandgap voltage reference

Abbasizadeh, Hamed; Hayder, Abbas Syed; Lee, K.Y.

doi:10.1049/el.2016.0193

Cited by 9 publications

(10 citation statements)

References 4 publications

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“…2(b). LDOs can provide a more precise and ripple-free supply voltage and current to a load circuit with much less area overhead than switching mode power converters (buck converters) [36]- [39]. They are considered as a better candidate for PoL power supply.…”

Section: B Linear Converters (Low Dropout Regulatorsmentioning

confidence: 99%

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: B Linear Converters (Low Dropout Regulatorsmentioning

confidence: 99%

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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“…Therefore, the proposed circuit can be considered as a class-AB OTA. The adopted ABC is composed of a modified version of the source follower, named the flipped voltage follower (FVF) [19][20][21]. This technique offers high current sourcing capability with very low output impedance and lowvoltage operation.…”

Section: Proposed Otamentioning

confidence: 99%

“…The operational trans-conductance amplifier (OTA) is one of the most widely used building blocks in analog design [1][2][3][4][5][6][7][8]. OTA can be used in low-voltage, low-power, and high-speed applications such as continuous-time Gm-C filters, switched-capacitor circuits, data converters, biomedical implants, signal conditioning of sensors, voltage regulators, and RF receivers [9][10][11][12][13][14][15][16][17][18][19][20]. In these applications, OTAs should have high values for DC-gain, slew rate (SR), and unity-gain bandwidth (UGBW) [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

84 dB DC‐gain two‐stage class‐AB OTA

Anisheh

Abbasizadeh

Shamsi

et al. 2019

IET Circuits, Devices & Systems

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Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

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“…Operational amplifiers (op-amps) are used in many mixed-mode systems [36][37][38][39]. The schematic of the two-stage op-amp is shown in Fig.…”

Section: Two-stage Op-ampmentioning

confidence: 99%

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Anisheh

Shamsi

2018

IET Circuits, Devices & Systems

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This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

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Highly accurate capacitor‐free LDO with sub‐1 V −120 dB PSRR bandgap voltage reference

Cited by 9 publications

References 4 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

84 dB DC‐gain two‐stage class‐AB OTA

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

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