Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias

Inoue, Fumihiro; Shimizu, Tomohiro; Miyake, Hiroshi; Arima, Ryohei; Iwamoto, Toshihiko; Seki, Hirofumi; Shinozaki, Yuko; Yamamoto, Tomohiko; Shingubara, Shoso

doi:10.1016/j.mee.2013.01.009

Cited by 25 publications

(22 citation statements)

References 17 publications

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“…It also shows some scallops formed by iterative passivation-etching process, which will be neglected in our simulations. SEM picture in [3] also shows a tapering structure.…”

Section: Introductionmentioning

confidence: 89%

“…Tapering effect refers to the empirical observation that the diameter of the TSV shrinks as it penetrates deeper into the silicon substrate, making the TSV non-cylindrical. Fig.1 illustrates the tapering effect by showing experimental data from [1] [3]. SEM pictures in [1] reveals a tapered TSV with a top diameter of 10.5μm, a height of 51.4μm, and a tapering angle of 89 • .…”

Section: Introductionmentioning

confidence: 99%

“…SEM pictures in [1] reveals a tapered TSV with a top diameter of 10.5μm, a height of 51.4μm, and a tapering angle of 89 • . [3] shows a tapered TSV with top diameter ≈ 5.8μm, height≈ 22.2μm, bottom diameter ≈ 3.2μm, tapering angle ≈ 87 • . Basically, the tapering effect causes TSVs to resemble a cone with the bottom region being thinner than the top region.…”

Section: Introductionmentioning

confidence: 99%

“…For example, tapered profile helps in conformal metal deposition resulting in better manufacturability [5]. According to some previous experimental data( [1], [3], [6], [11]), the TSV taper angle Θ could vary from 85 o to 90 o . A mere 3 o reduction of Θ (see Fig.2(f)) from the ideal value of 90 o causes significant variation between the top and bottom surface areas.…”

Section: Introductionmentioning

confidence: 99%

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Detailed electrical and reliability study of tapered TSVs

Srivastava

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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This paper investigates the TSV's tapering effect, an inevitable byproduct of the non-ideal Dry Reactive Ion Etching based manufacturing, and its impact on the TSV's electrical performance and reliability properties. For TSV's electrical performance, we show that the TSV delay (estimated by the Elmore model) is not bidirectionally symmetric for a tapered TSV. For TSV's reliability property, current density, thermal mechanical stress, and TSV heating are primary concerns in this paper. We show that the current density and thermal mechanical stress distribution inside the TSV are more nonuniform in realistic tapered TSVs than ideal cylindrical TSVs, both of which lead to faster material fatigue as well as severe electromigration. However, the TSV tapering effect helps us save significant routing areas on the narrower side of the TSV because less Keep Out Zone (KOZ) is needed. The overheating problem becomes significant in 3D-ICs mainly because the oxide layer and bonding materials are usually very poor heat conductors. Furthermore, we set up coupled mass transport equations to estimate TSV's electromigration, based on the current and stress simulation, and produce a MTTF (Mean Time to Failure) map of all positions in TSVs and neighboring areas and this helps us easily recognize the most vulnerable positions in a 3D structure, which could be further optimized during manufacturing and design.Finally, we show our tapered TSV simulations' implications on TSV's modeling, clock network design, and algorithms for gate placement and wire routing. The compact TSV's model and clock network design must take into account the tapering effect, given that signals delay in one direction is significantly slower than the other direction. Cell placement and routing algorithms should treat TSV as obstacles, with different sizes on the top and the bottom layers.

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“…It also shows some scallops formed by iterative passivation-etching process, which will be neglected in our simulations. SEM picture in [3] also shows a tapering structure.…”

Section: Introductionmentioning

confidence: 89%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Detailed electrical and reliability study of tapered TSVs

Srivastava

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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“…One important aspect that has seldom been investigated is the TSV tapering effect. TSV tapering effect refers to the empirical observation that the diameter of the TSV shrinks as it penetrates deeper into the substrate, making the TSV resembles a cone rather than an ideal cylinder [1], [4], [6], [10]. The TSV tapering effect is a natural result of the deep reactive ion etching (DRIE)-based TSV manufacturing process.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Layout Optimization for Tapered TSVs

Srivastava

2015

IEEE Trans. VLSI Syst.

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Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering effect (which is an inevitable byproduct of deep reactive Ion etchingbased manufacturing) and its impact on the TSVs electrical properties. We show that the current crowding effect is more severe in realistic tapered TSVs than ideal cylindrical TSVs. We propose a nonuniform current density model for tapered TSVs, which achieves considerable accuracy and speedup in estimating the current density distribution, when compared with the existing models developed for cylindrical TSVs. We apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing problem to minimize TSV-involved path delay under second-order delay model while keeping the peak current density within tolerable levels. A new dynamic programming-based heuristic is proposed to find the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.

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Metallization of Semiconductors and Nonconductive Surfaces from Aqueous Solutions

Djokić¹,

Magagnin

2014

Electrodeposition and Surface Finishing

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Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias

Cited by 25 publications

References 17 publications

Detailed electrical and reliability study of tapered TSVs

Detailed electrical and reliability study of tapered TSVs

Modeling and Layout Optimization for Tapered TSVs

Metallization of Semiconductors and Nonconductive Surfaces from Aqueous Solutions

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