Highly endurable floating body cell memory: Vertical biristor

Moon, Dong‐Il; Choi, Sung-Jin; Kim, Jee-Yeon; Ko, Sangjin; Kim, Moon-Seok; Oh, Jin Kyung; Lee, Gi-Sung; Kang, Min-Ho; Kim, Young-Su; Kim, Jeoung-Woo; Choi, Yang‐Kyu

doi:10.1109/iedm.2012.6479147

Cited by 17 publications

(8 citation statements)

References 1 publication

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“…9 shows the I C -V CE characteristics of the optimized SALTran biristor compared with those of the un-optimized SALTran biristor of well as an improvement in the latch window in the optimized SALTran biristor. The conventional biristors have identical emitter and collector dopings, which enables bi-directional operation and hence, results in sneak leakage paths among the neighboring cells in a crossbar array [3], [4]. However, in the proposed SALTran biristor, the emitter doping has to be necessarily lower than the collector doping to achieve a higher current gain and therefore, a higher impact ionization.…”

Section: Resultsmentioning

confidence: 99%

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A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis

Kumar

Maheedhar

Varma

2015

IEEE J. Electron Devices Soc.

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In this paper, using 2-D simulations, we report a silicon biristor with reduced operating voltage using the surface accumulation layer transistor (SALTran) concept. The electrical characteristics of the proposed SALTran biristor are simulated and compared with that of a conventional silicon biristor with identical dimensions. The proposed device is optimized with respect to the device parameters to ensure a reasonable latch window while maintaining low latch voltages. Our results demonstrate that the SALTran biristor exhibits a latch-up voltage of 2.14 V and a latch-down voltage of 1.68 V leading to a 57% lower operating voltage compared to the conventional silicon biristor.INDEX TERMS Biristor, bistable resistor, open-base breakdown, current gain, surface accumulation layer transistor (SALTran) effect, device optimization.

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Section: Resultsmentioning

confidence: 99%

“…The biristor was studied as a biosensor [5] and can be a promising candidate in terms of CMOS compatibility, low-cost, and compact density. It is also free of cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure, unlike 1T-DRAM [3].…”

Section: Introductionmentioning

confidence: 99%

A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis

Kumar

Maheedhar

Varma

2015

IEEE J. Electron Devices Soc.

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“…As long as its sizes are reasonably scaled and optimized, this issue could be inconsequential [7]. It is worthwhile to note that the gateless biristor is analogous to an open-base BJT and that the gated 1T-DRAM is a conventional MOSFET, i.e., akin to a gated BJT.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Bias Schemes for Long-Term Endurable 1T-DRAM Through the Use of the Biristor Mode Operation

Kim

Moon

Choi

2014

IEEE Electron Device Lett.

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The long-term endurance characteristics are investigated for MOSFET-based capacitorless one-transistor DRAM (1T-DRAM) under the conventional versus biristor mode. Based on the experimental results and on a supporting simulation study, it was found that the MOSFET-based 1T-DRAM, when enabled by a biristor mode, is preferred for long-term endurance compared with MOSFET-based 1T-DRAM when operated in a conventional mode. Although a high drain voltage is required in the biristor mode for programming, improved endurance characteristics are observed. The simulation study showed that this feature is achieved by the suppression of hot-hole-induced degradation, which arises from the absence of a gate use at the dynamic cell. Thus, this letter provides a new type of device architecture as well as a novel and innovative operational method pertaining to conventional 1T-DRAM to mitigate the problem of limited endurance.

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“…From a structural point of view, such a biristor is categorized into two groups. One is a planar structure that was implemented on a silicon-on-insulator (SOI) wafer [7,8] for a floating body and the other is a vertical structure that was fabricated on a bulk-Si wafer [9,10]. In the vertical biristor, a p-type floating body located at the middle of the pillar was inherently made by n-type junctions positioned at a top and bottom of a pillar.…”

Section: Introductionmentioning

confidence: 99%

Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure

et al. 2021

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For the first time, a novel germanium (Ge) bi-stable resistor (biristor) with a vertical pillar structure was implemented on a bulk substrate. The basic structure of the Ge pillar-typed biristor is a p-n-p bipolar junction transistor (BJT) with an open base (floating), which is equivalent to a gateless p-channel metal oxide semiconductor field-effect transistor (MOSFET). In the pillar formation, we adopted an amorphous carbon layer to protect the Ge surface from both physical and chemical damage by subsequent processes. A hysteric current-voltage (I-V) characteristic, which results in a sustainable binary state, i.e., high current and low current at the same voltage, can be utilized for a memory device. A lower operating voltage with high current was achieved, compared to a Si biristor, due to the low energy bandgap of pure Ge.

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Highly endurable floating body cell memory: Vertical biristor

Cited by 17 publications

References 1 publication

A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis

A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis

Optimization of Bias Schemes for Long-Term Endurable 1T-DRAM Through the Use of the Biristor Mode Operation

Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure

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