In this paper, using 2-D simulations, we report a novel junction-less biristor in which the emitter and collector regions are created by applying the charge plasma concept on a P-doped silicon film. Since no chemical doping is required, the junction-less biristor can be realized with a low thermal budget. We demonstrate that the junction-less biristor exhibits not only a significant low latch-up voltage (2.0 V) but also has a large latch window (0.66 V) when compared to that of a conventional silicon biristor with similar parameters. The reasons for this improved performance are discussed.INDEX TERMS Biristor, junction-less, bistable resistor, current gain, SALTran effect.

The X10 programming language is organized around the notion of places (an encapsulation of data and activities operating on the data), partitioned global address space (PGAS), and asynchronous computation and communication. This paper introduces an expressive subset of X10, Flat X10, designed to permit efficient execution across multiple single-threaded places with a simple runtime and without compromising on the productivity of X10. We present the design, implementation and evaluation of a compiler and runtime system for Flat X10. The Flat X10 compiler translates programs into C++ SPMD programs communicating using an active messaging infrastructure. It uses novel techniques to transform explicitly parallel programs into SPMD programs. The runtime system is based on IBM's LAPI (Low-level API) and is easily portable to other libraries such as GASNet and ARMCI. Our implementation realizes performance comparable to hand-written MPI programs for well-known HPC benchmarks such as Random Access, Stream, and FFT, on a Federation-based cluster of Power5 SMPs (with hundreds of processors) and the Blue Gene (with thousands of processors). Submissions based on the work presented in this paper were co-winners of the 2007 and 2008 HPC Challenge Type II Awards.

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In this brief, we report a novel metalsemiconductor-metal-based bistable resistor, called the Schottky biristor, whose performance is superior to the existing bipolar junction transistor-based biristors. The proposed device can be realized by joining symmetrical Schottky contacts back to back. Apart from being free of the thermal budgets involved in the fabrication of p-n junctions in a biristor, the Schottky biristor also has much lower latch voltages (latch-up voltage of 1.62 V and latch-down voltage of 1.18 V) and a reasonable latch window (0.44 V) as demonstrated by our simulation results.

In this paper, using 2-D simulations, we report a silicon biristor with reduced operating voltage using the surface accumulation layer transistor (SALTran) concept. The electrical characteristics of the proposed SALTran biristor are simulated and compared with that of a conventional silicon biristor with identical dimensions. The proposed device is optimized with respect to the device parameters to ensure a reasonable latch window while maintaining low latch voltages. Our results demonstrate that the SALTran biristor exhibits a latch-up voltage of 2.14 V and a latch-down voltage of 1.68 V leading to a 57% lower operating voltage compared to the conventional silicon biristor.INDEX TERMS Biristor, bistable resistor, open-base breakdown, current gain, surface accumulation layer transistor (SALTran) effect, device optimization.