Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

Anwer, Jahanzeb; Khalid, Usman; Singh, Narinderjit; Hamid, Nor Hisham; Asirvadam, Vijanth S.

doi:10.1109/icectech.2010.5479997

Cited by 7 publications

(5 citation statements)

References 6 publications

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“…Simulations ( [10], [12]) show that modeling thermal noise in a circuit cause many unnecessary bit reversals in simple CMOS gate as compared to almost noiseless output of MRF-CMOS gate. The drawback of this technique is an immense increase in the number of transistors required for a simple circuit [10].…”

Section: A Markov Random Field (Mrf) Modelmentioning

confidence: 98%

“…Between these two schemes, MRF was proved to be better than redundancy in terms of reliability, error-handling capability and area efficiency [11]. The premier research on MRF based circuit design is extended at the design, simulation framework and implementation stages in [11][12][13][14]. The redesigned MRF is termed as 'Improved-MRF' circuit design.…”

Section: Introductionmentioning

confidence: 99%

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Reliable area index: A novel approach to measure reliability of Markov Random Field based circuits

Anwer

Shaukat

Khalid

et al. 2012

2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)

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Markov Random Field (MRF) is a probabilistic circuit design approach that transforms simple CMOS to MRF-CMOS digital circuits. The transformed circuits are proved to be extremely noise-tolerant in the previous research literature. In this paper, we have quantified the noise tolerance capability of MRF circuits as compared to CMOS counterparts. The tradeoff for this noise-immunity is the increase in transistor-count of the circuit. This tradeoff is modelled by a novel factor in this research work called as 'reliable area index'. The results show that the value of this index is 30 times higher for MRF than CMOS which proves that the MRF design approach still maintains a suitable tradeoff between noise-tolerance and area overhead of the circuit.

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Section: A Markov Random Field (Mrf) Modelmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Reliable area index: A novel approach to measure reliability of Markov Random Field based circuits

Anwer

Shaukat

Khalid

et al. 2012

2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)

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“…But, for improved circuit reliability, high transistor count is the price a circuit designer has to pay. (Interested readers can find MRF mathematical model in [5] and transformation method of CMOS to MRF-CMOS in [4]). …”

Section: B Markov Random Field(mrf) Modelmentioning

confidence: 99%

“…Simulations ( [3] and [4]) show that modeling thermal noise in a circuit result in many unnecessary bit reversals in simple CMOS gate. The drawback of this technique is the immense increase in the number of transistors required for a simple CMOS gate as compared to almost noiseless output of MRFcircuit.…”

Section: B Markov Random Field(mrf) Modelmentioning

confidence: 99%

“…For example, the MRF-CMOS inverter requires 34 transistors in contrast to the 2 transistors required for a simple CMOS inverter. Another disadvantage is the difficulty to model this technique into software tools due to its complex implementation model and need to divert from system-level perspective to componentlevel for cost-effective system design [4].…”

Section: J Multiple Environment and Multiple Error Simulation Tool Formentioning

confidence: 99%

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Fault-tolerance and noise modelling in nanoscale circuit design

Anwer

Fayyaz

Masud

et al. 2010

2010 International Symposium on Signals, Systems and Electronics

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Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance in low-scaled transistor operation of future CMOS technology models. This paper is destined to give an overview of all the major fault-tolerance techniques and noise models proposed so far. Summing and analysing all this work, we have divided the literature into three categories and discussed their applicability in terms of proposing circuit design modifications, finding output error probability or methods proposed to achieve highly accurate simulation results.

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