Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

Lim, Kwan-Yong; Sung, Min-Gyu; Cho, Heung-Jae; Kim, Yong Soo; Jang, Se-Aug; Oh, Jae‐Geun; Lee, Seung Ryong; Kim, Kwang-Ok; Lee, Pilsoo; Chun, Yunseok; Yang, Heesu; Kwak, Noh-Jung; Sohn, Hyunchul; Kim, Jinwoong; Park, Sung Wook

doi:10.1109/vlsit.2006.1705223

Cited by 2 publications

(1 citation statement)

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“…The gate re-oxidation that is performed in H 2 O/H 2 ambient at high temperature for selectivity improves gate oxide integrity (GOI) and also reduces gate induced drain leakage current (GIDL). In this case, abnormal oxidation of these barrier metals occurring during the selective re-oxidation process, could be minimized by pre-capping Si-N film during the gate poly-etch process [3]. Detailed conventional process flow of tungsten dual-poly gate stack formation is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device

Sung¹,

Kim²,

Park³

2011

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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We investigated the mechanism of stress-induced self-aligned contact (SAC) failure in the sub-60 nm W-dual poly metal gate process in DRAM devices. It was found that during NH 3 pre-purge step of gate capping nitride deposition, amorphous WN x barrier and side of gate etched W electrode were transformed into tensile crystallized W 2 N, which relieves high compressive stress of inner gate W. Asymmetrical relief of W stress could create torque leading to gate leaning which is a main culprit of SAC failure during reliability test. Therefore, by reducing NH 3 pre-purge time, we successfully could reduce gate leaning which endures good reliability characteristics

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Section: Introductionmentioning

confidence: 99%