The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (t bd ) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, t bd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter t bd than with DC at a lower frequency. This is attributed to hole trapping into IL as V g is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer t bd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because G m degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.

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Due to the increased physical dielectric thickness and reduced gate leakage in metal-gate/high-k devices, degradation caused by channel hot carriers (HCs) becomes more significant than positive bias temperature stress. In an analysis of metal-gate/high-k devices, accelerated channel HCs were found to induce permanent interface damage. Moreover, the overall threshold voltage shifts caused by HC stress were enhanced at higher temperatures, which is due to an association with positive bias temperature instability. Therefore, high-temperature HC stress has emerged as a dominant degradation factor in short-channel nMOSFETs with metal-gate/high-k dielectrics.Index Terms-Hot carrier (HC), metal-gate/high-k dielectrics, positive bias temperature instability (PBTI).

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling.Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.