Technology scaling on High-K &amp;amp; Metal-Gate FinFET BTI reliability

Lee, Kyong Taek; Kang, Wonchang; Chung, Eun-Ae; Kim, Gunrae; Shim, Hyungjoon; Lee, Hyun–Woo; Kim, Hye-Jin; Choe, Minhyeok; Lee, Nae-In; Patel, Anuj; Park, Junekyun; Park, Jongwoo

doi:10.1109/irps.2013.6531956

Cited by 26 publications

(5 citation statements)

References 13 publications

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“…We modelled degradations and improvements in routing resources with the model (10). We note in Table 4 the parameters γ, Ea and b, which are similar for all RO architectures.…”

Section: Modelling Routing Resources Degradations Under Static Stressmentioning

confidence: 99%

“…Intel also shows in [ 9 ] that PBTI decreases in the 22 nm FinFET compared with the 32 nm HKMG MOSFET; however, a slight increase in NBTI is observed in the FinFET. In [ 10 ], the author reveals that the NBTI recovery mechanism is more important in a 20 nm MOSFET than in a 14 nm FinFET, which may explain why the overall degradation due to NBTI is greater in the FinFET [ 9 ]. A simulation based on the diffusion–reaction model of a 16 nm MOSFET and FinFET is performed in [ 11 ] and indicates that the propagation delay degradation is

higher in MOSFET.…”

Section: Introductionmentioning

confidence: 99%

“…It is expensive to monopolise such a test bench with access to the transistor, so most of the degradation measurements are carried out for less than 10,000 s (≈3 h) [ 10 , 12 , 16 , 17 ]. In order to observe degradation over a short test period, the ageing conditions applied are far from operational conditions.…”

Section: Introductionmentioning

confidence: 99%

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Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Sobas,

Marc

2023

Micromachines

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Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

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“…We modelled degradations and improvements in routing resources with the model (10). We note in Table 4 the parameters γ, Ea and b, which are similar for all RO architectures.…”

Section: Modelling Routing Resources Degradations Under Static Stressmentioning

confidence: 99%

higher in MOSFET.…”

Section: Introductionmentioning

confidence: 99%

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Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Sobas,

Marc

2023

Micromachines

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“…Aging related degradation mechanisms like NBTI are strongly a function of workload/activity pattern at the gate input of the transistor due to the observed recovery effects [4], [13]. In [10], an Adaptive Workload Splitting (AWS) algorithm and a long-term extrapolation methodology were proposed for fast calculation of NBTI degradation due to an arbitrary nonuniform activity pattern with excellent accuracy.…”

Section: A the Proposed Workload Dependent Aging Aware Design Flowmentioning

confidence: 99%

Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm

Mishra

Weckx

Zografos

et al. 2021

2021 IEEE International Reliability Physics Symposium (IRPS)

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Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of environmental variations (Voltage, Temperature) and manufacturing Process variations. On top of these PVT variations, aging related parametric drift (e.g. due to BTI, HCI) also limits performance by requiring additional timing margin. In principle, corner based design methodology can be adopted. However, this approach is sub-optimal, because it applies margins which may be either too optimistic or pessimistic since it tends to ignore the correlation effects which exist inherently due to the circuit topology and the workload effects. In this paper, we propose a workload-dependent reliability aware optimization flow under the influence of NBTI aging by utilizing an optimal margining scheme. The proposed flow takes into account the relevant correlations in a design by modelling the degradation accurately and thus enables achieving the desired Power-Performance-Area (PPA) goals without severe reliability penalty.

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“…Figure 3.12 shows the absolute shift of the V T for a 14nm pFinFET at 125 • C under the time and voltage acceleration. Figure 3.12: V T shift due to BTI under time and voltage acceleration in 14nm pFinFET [84] It has been shown that BTI recovery in tri-gate devices matches data and model predictions from planar devices [85], also just as in planar devices increasing temperature can enhance the recovery in tri-gate devices [86]. Regarding these, Figure 3.13 shows the recovery characteristics between planer (20nm) and FinFET devices (14nm).…”

Section: Reliability-aware Memory Design Using Advanced Reconfigurati...mentioning

confidence: 61%

Reliability-aware memory design using advanced reconfiguration mechanisms

Pouyan

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Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens. Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suceda

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Technology scaling on High-K & Metal-Gate FinFET BTI reliability

Cited by 26 publications

References 13 publications

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm

Reliability-aware memory design using advanced reconfiguration mechanisms

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